Cyclone® V 5CEA7 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CEA7 FPGA 5CEFA7U19C8N

  • MM# 965683
  • Spec Code SR4RJ
  • Ordering Code 5CEFA7U19C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7U19I7

  • MM# 965684
  • Spec Code SR4RK
  • Ordering Code 5CEFA7U19I7
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F23C8N

  • MM# 965951
  • Spec Code SR4ZD
  • Ordering Code 5CEFA7F23C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F27C6N

  • MM# 965952
  • Spec Code SR4ZE
  • Ordering Code 5CEFA7F27C6N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F31C7N

  • MM# 965953
  • Spec Code SR4ZF
  • Ordering Code 5CEFA7F31C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7F27C8N

  • MM# 967846
  • Spec Code SR6KT
  • Ordering Code 5CEBA7F27C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7F31C7N

  • MM# 967847
  • Spec Code SR6KU
  • Ordering Code 5CEBA7F31C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7M15C6N

  • MM# 967865
  • Spec Code SR6L3
  • Ordering Code 5CEFA7M15C6N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F23I7N

  • MM# 967866
  • Spec Code SR6L2
  • Ordering Code 5CEFA7F23I7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7U19C6N

  • MM# 967867
  • Spec Code SR6L5
  • Ordering Code 5CEFA7U19C6N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7U19A7N

  • MM# 967868
  • Spec Code SR6L4
  • Ordering Code 5CEFA7U19A7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7F23C7N

  • MM# 968186
  • Spec Code SR6V9
  • Ordering Code 5CEBA7F23C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7F23C8N

  • MM# 968187
  • Spec Code SR6VA
  • Ordering Code 5CEBA7F23C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7F27C7N

  • MM# 968188
  • Spec Code SR6VB
  • Ordering Code 5CEBA7F27C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7U19C8N

  • MM# 968189
  • Spec Code SR6VC
  • Ordering Code 5CEBA7U19C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F31I7N

  • MM# 968205
  • Spec Code SR6VU
  • Ordering Code 5CEFA7F31I7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7M15C8N

  • MM# 968339
  • Spec Code SR6ZQ
  • Ordering Code 5CEBA7M15C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F31C8N

  • MM# 968346
  • Spec Code SR6ZX
  • Ordering Code 5CEFA7F31C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7M15C8N

  • MM# 968347
  • Spec Code SR6ZY
  • Ordering Code 5CEFA7M15C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F23C7N

  • MM# 968896
  • Spec Code SR7FT
  • Ordering Code 5CEFA7F23C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F27C7N

  • MM# 968897
  • Spec Code SR7FU
  • Ordering Code 5CEFA7F27C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7M15C7N

  • MM# 968898
  • Spec Code SR7FV
  • Ordering Code 5CEFA7M15C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7M15C7N

  • MM# 968911
  • Spec Code SR7FJ
  • Ordering Code 5CEBA7M15C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7U19C7N

  • MM# 970592
  • Spec Code SR8U7
  • Ordering Code 5CEBA7U19C7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F27C8N

  • MM# 970596
  • Spec Code SR8UB
  • Ordering Code 5CEFA7F27C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F31C6N

  • MM# 970597
  • Spec Code SR8UC
  • Ordering Code 5CEFA7F31C6N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7U19I7N

  • MM# 970598
  • Spec Code SR8UD
  • Ordering Code 5CEFA7U19I7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEBA7F31C8N

  • MM# 973738
  • Spec Code SRBM5
  • Ordering Code 5CEBA7F31C8N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F23C6N

  • MM# 973744
  • Spec Code SRBMB
  • Ordering Code 5CEFA7F23C6N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F27I7

  • MM# 973745
  • Spec Code SRBMC
  • Ordering Code 5CEFA7F27I7
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7F27I7N

  • MM# 973746
  • Spec Code SRBMD
  • Ordering Code 5CEFA7F27I7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7M15I7N

  • MM# 973747
  • Spec Code SRBME
  • Ordering Code 5CEFA7M15I7N
  • Stepping A1

Cyclone® V 5CEA7 FPGA 5CEFA7U19C7N

  • MM# 973748
  • Spec Code SRBMF
  • Ordering Code 5CEFA7U19C7N
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR6VU

SR6ZY

SR6ZX

SR7FJ

SR8U7

SR6VC

SR6VB

SR6VA

SR4ZF

SR6KU

SR4ZE

SR6KT

SR6L5

SR4RK

SR6ZQ

SR4RJ

SR4ZD

SR6L4

SR6L3

SR6L2

SRBMF

SRBME

SR6V9

SRBMD

SRBMC

SRBMB

SR7FU

SR8UC

SR7FT

SR8UB

SRBM5

SR7FV

SR8UD

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.