Cyclone® V 5CEA9 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CEA9 FPGA 5CEBA9F31C7N

  • MM# 965677
  • Spec Code SR4RD
  • Ordering Code 5CEBA9F31C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F31C7N

  • MM# 965685
  • Spec Code SR4RL
  • Ordering Code 5CEFA9F31C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEBA9F27C7N

  • MM# 965942
  • Spec Code SR4Z4
  • Ordering Code 5CEBA9F27C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F31C8N

  • MM# 965955
  • Spec Code SR4ZG
  • Ordering Code 5CEFA9F31C8N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9U19C8N

  • MM# 965956
  • Spec Code SR4ZH
  • Ordering Code 5CEFA9U19C8N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEBA9U19C7N

  • MM# 967848
  • Spec Code SR6KV
  • Ordering Code 5CEBA9U19C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9U19C7N

  • MM# 967870
  • Spec Code SR6L6
  • Ordering Code 5CEFA9U19C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEBA9F23C8N

  • MM# 968190
  • Spec Code SR6VD
  • Ordering Code 5CEBA9F23C8N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEBA9F27C8N

  • MM# 968191
  • Spec Code SR6VE
  • Ordering Code 5CEBA9F27C8N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEBA9F31C8N

  • MM# 968192
  • Spec Code SR6VF
  • Ordering Code 5CEBA9F31C8N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F23C7N

  • MM# 968206
  • Spec Code SR6VV
  • Ordering Code 5CEFA9F23C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F27I7N

  • MM# 968207
  • Spec Code SR6VW
  • Ordering Code 5CEFA9F27I7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9U19I7N

  • MM# 968208
  • Spec Code SR6VX
  • Ordering Code 5CEFA9U19I7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F23I7N

  • MM# 968348
  • Spec Code SR6ZZ
  • Ordering Code 5CEFA9F23I7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F23C8N

  • MM# 968899
  • Spec Code SR7FW
  • Ordering Code 5CEFA9F23C8N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F31I7N

  • MM# 968900
  • Spec Code SR7FX
  • Ordering Code 5CEFA9F31I7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9U19A7N

  • MM# 968901
  • Spec Code SR7FY
  • Ordering Code 5CEFA9U19A7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEBA9F23C7N

  • MM# 973739
  • Spec Code SRBM6
  • Ordering Code 5CEBA9F23C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEBA9U19C8N

  • MM# 973740
  • Spec Code SRBM7
  • Ordering Code 5CEBA9U19C8N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F27C7N

  • MM# 973749
  • Spec Code SRBMG
  • Ordering Code 5CEFA9F27C7N
  • Stepping A1

Cyclone® V 5CEA9 FPGA 5CEFA9F27C8N

  • MM# 973750
  • Spec Code SRBMH
  • Ordering Code 5CEFA9F27C8N
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR6VV

SR6ZZ

SRBMH

SRBMG

SR6VX

SR6VW

SR4RD

SR6VF

SR6VE

SR6VD

SR4ZH

SR4ZG

SR6KV

SR6L6

SR4RL

SR4Z4

SRBM7

SRBM6

SR7FY

SR7FX

SR7FW

Drivers and Software

Latest Drivers & Software

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Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.