Cyclone® V 5CEA5 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CEA5 FPGA 5CEBA5U19C7N

  • MM# 965676
  • Spec Code SR4RC
  • Ordering Code 5CEBA5U19C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5F23C6N

  • MM# 965681
  • Spec Code SR4RH
  • Ordering Code 5CEFA5F23C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5F23C8N

  • MM# 965949
  • Spec Code SR4ZB
  • Ordering Code 5CEFA5F23C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5U19C6N

  • MM# 965950
  • Spec Code SR4ZC
  • Ordering Code 5CEFA5U19C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5U19I7N

  • MM# 967864
  • Spec Code SR6L1
  • Ordering Code 5CEFA5U19I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEBA5U19C8N

  • MM# 968185
  • Spec Code SR6V8
  • Ordering Code 5CEBA5U19C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5F23C7N

  • MM# 968195
  • Spec Code SR6VJ
  • Ordering Code 5CEFA5F23C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5M13C6N

  • MM# 968196
  • Spec Code SR6VK
  • Ordering Code 5CEFA5M13C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CEA5 FPGA 5CEFA5M13I7N

  • MM# 968197
  • Spec Code SR6VL
  • Ordering Code 5CEFA5M13I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CEA5 FPGA 5CEBA5F23C7N

  • MM# 968337
  • Spec Code SR6ZN
  • Ordering Code 5CEBA5F23C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5M13C7N

  • MM# 968345
  • Spec Code SR6ZW
  • Ordering Code 5CEFA5M13C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CEA5 FPGA 5CEFA5M13C8N

  • MM# 968893
  • Spec Code SR7FQ
  • Ordering Code 5CEFA5M13C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CEA5 FPGA 5CEFA5U19C7N

  • MM# 968894
  • Spec Code SR7FR
  • Ordering Code 5CEFA5U19C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5U19C8N

  • MM# 968895
  • Spec Code SR7FS
  • Ordering Code 5CEFA5U19C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEBA5F23C8N

  • MM# 973737
  • Spec Code SRBM4
  • Ordering Code 5CEBA5F23C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5F23I7N

  • MM# 973742
  • Spec Code SRBM9
  • Ordering Code 5CEFA5F23I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CEA5 FPGA 5CEFA5U19A7N

  • MM# 973743
  • Spec Code SRBMA
  • Ordering Code 5CEFA5U19A7N
  • Stepping A1
  • ECCN 3A991

Trade compliance information

  • ECCN Varies By Product
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SRBMA

SR6ZW

SR4ZC

SR4ZB

SR6L1

SR6V8

SR4RC

SR7FS

SR7FR

SR7FQ

SRBM9

SR6VL

SR6VK

SR4RH

SR6VJ

SR6ZN

SRBM4

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.