Intel® 82P43 Graphics and Memory Controller Hub
Compare Intel® Products
Max CPU Configuration
34mm x 34mm
Security & Reliability
Ordering and Compliance
Legacy Intel® Core™ Processors
Legacy Intel® Pentium® Processor
Legacy Intel® Celeron® Processor
Drivers and Software
The date the product was first introduced.
FSB (Front Side Bus) is the interconnect between the processor and the Memory Controller Hub (MCH).
FSB parity provides error checking on data sent on the FSB (Front Side Bus).
Thermal Design Power (TDP) represents the average power, in watts, the processor dissipates when operating at Base Frequency with all cores active under an Intel-defined, high-complexity workload. Refer to Datasheet for thermal solution requirements.
Embedded Options Available
Embedded Options Available indicates products that offer extended purchase availability for intelligent systems and embedded solutions. Product certification and use condition applications can be found in the Production Release Qualification (PRQ) report. See your Intel representative for details.
Intel® processors come in four different types: Single Channel, Dual Channel, Triple Channel, and Flex Mode. Maximum supported memory speed may be lower when populating multiple DIMMs per channel on products that support multiple memory channels.
Max # of Memory Channels
The number of memory channels refers to the bandwidth operation for real world application.
Physical Address Extensions
Physical Address Extensions (PAE) is a feature that allows 32-bit processors to access a physical address space larger than 4 gigabytes.
ECC Memory Supported ‡
ECC Memory Supported indicates processor support for Error-Correcting Code memory. ECC memory is a type of system memory that can detect and correct common kinds of internal data corruption. Note that ECC memory support requires both processor and chipset support.
Integrated Graphics ‡
Integrated graphics allow for incredible visual quality, faster graphic performance and flexible display options without the need for a separate graphics card.
Intel® Clear Video Technology
Intel® Clear Video Technology is a suite of image decode and processing technologies built into the integrated processor graphics that improve video playback, delivering cleaner, sharper images, more natural, accurate, and vivid colors, and a clear and stable video picture.
PCI Express Revision
PCI Express Revision is the supported version of the PCI Express standard. Peripheral Component Interconnect Express (or PCIe) is a high-speed serial computer expansion bus standard for attaching hardware devices to a computer. The different PCI Express versions support different data rates.
PCI Express Configurations ‡
PCI Express (PCIe) Configurations describe the available PCIe lane configurations that can be used to link to PCIe devices.
Max # of PCI Express Lanes
A PCI Express (PCIe) lane consists of two differential signaling pairs, one for receiving data, one for transmitting data, and is the basic unit of the PCIe bus. Max # of PCI Express Lanes is the total number of supported lanes.
Case Temperature is the maximum temperature allowed at the processor Integrated Heat Spreader (IHS).
Intel® Virtualization Technology for Directed I/O (VT-d) ‡
Intel® Virtualization Technology for Directed I/O (VT-d) continues from the existing support for IA-32 (VT-x) and Itanium® processor (VT-i) virtualization adding new support for I/O-device virtualization. Intel VT-d can help end users improve security and reliability of the systems and also improve performance of I/O devices in virtualized environments.
Intel® Fast Memory Access
Intel® Fast Memory Access is an updated Graphics Memory Controller Hub (GMCH) backbone architecture that improves system performance by optimizing the use of available memory bandwidth and reducing the latency of the memory accesses.
Intel® Flex Memory Access
Intel® Flex Memory Access facilitates easier upgrades by allowing different memory sizes to be populated and remain in dual-channel mode.
Intel® Trusted Execution Technology ‡
Intel® Trusted Execution Technology for safer computing is a versatile set of hardware extensions to Intel® processors and chipsets that enhance the digital office platform with security capabilities such as measured launch and protected execution. It enables an environment where applications can run within their own space, protected from all other software on the system.
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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for informational purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.
System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.