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The date the product was first introduced.
FSB (Front Side Bus) is the interconnect between the processor and the Memory Controller Hub (MCH).
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Thermal Design Power (TDP) represents the average power, in watts, the processor dissipates when operating at Base Frequency with all cores active under an Intel-defined, high-complexity workload. Refer to Datasheet for thermal solution requirements.
Embedded Options Available indicates products that offer extended purchase availability for intelligent systems and embedded solutions. Product certification and use condition applications can be found in the Production Release Qualification (PRQ) report. See your Intel representative for details.
Max memory size refers to the maximum memory capacity supported by the processor.
Intel® processors come in four different types: a Single Channel, Dual Channel, Triple Channel, and Flex Mode.
The number of memory channels refers to the bandwidth operation for real world application.
Max Memory bandwidth is the maximum rate at which data can be read from or stored into a semiconductor memory by the processor (in GB/s).
ECC Memory Supported indicates processor support for Error-Correcting Code memory. ECC memory is a type of system memory that can detect and correct common kinds of internal data corruption. Note that ECC memory support requires both processor and chipset support.
Integrated graphics allow for incredible visual quality, faster graphic performance and flexible display options without the need for a separate graphics card.
Graphics Output defines the interfaces available to communicate with display devices.
PCI Express Revision is the supported version of the PCI Express standard. Peripheral Component Interconnect Express (or PCIe) is a high-speed serial computer expansion bus standard for attaching hardware devices to a computer. The different PCI Express versions support different data rates.
PCI Express (PCIe) Configurations describe the available PCIe lane configurations that can be used to link to PCIe devices.
A PCI Express (PCIe) lane consists of two differential signaling pairs, one for receiving data, one for transmitting data, and is the basic unit of the PCIe bus. Max # of PCI Express Lanes is the total number of supported lanes.
Case Temperature is the maximum temperature allowed at the processor Integrated Heat Spreader (IHS).
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for informational purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.