Intel® 82X48 Memory Controller Hub
Specifications
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Essentials
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Product Collection
Intel® 4 Series Chipsets
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Code Name
Products formerly Bearlake
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Marketing Status
Discontinued
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Launch Date
Q1'08
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Supported FSBs
1600MHz / 1333MHz / 1066MHz / 800MHz
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Lithography
90 nm
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TDP
30.5 W
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Supplemental Information
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Embedded Options Available
No
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Datasheet
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Memory Specifications
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Max Memory Size (dependent on memory type)
8 GB
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Memory Types
DDR3 800/1066/1333, DDR2 667/800
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Max # of Memory Channels
2
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Max Memory Bandwidth
12.8 GB/s
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ECC Memory Supported ‡
No
GPU Specifications
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Integrated Graphics ‡
No
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Graphics Output
None
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Macrovision* License Required
No
Expansion Options
Package Specifications
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Max CPU Configuration
1
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TCASE
84°C
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Package Size
40mm x 40mm
Ordering and Compliance
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Retired and discontinued
Trade compliance information
- ECCN 4A994
- CCATS NA
- US HTS 8542310001
Compatible Products
Legacy Intel® Core™ Processors
Legacy Intel® Pentium® Processor
Legacy Intel® Celeron® Processor
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Supported FSBs
FSB (Front Side Bus) is the interconnect between the processor and the Memory Controller Hub (MCH).
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
TDP
Thermal Design Power (TDP) represents the average power, in watts, the processor dissipates when operating at Base Frequency with all cores active under an Intel-defined, high-complexity workload. Refer to Datasheet for thermal solution requirements.
Embedded Options Available
“Embedded Options Available” indicates the SKU is typically available for purchase for 7 years from the launch of the first SKU in the Product family and may be available for purchase for a longer period of time under certain circumstances. Intel does not commit or guarantee product Availability or Technical Support by way of roadmap guidance. Intel reserves the right to change roadmaps or discontinue products, software and software support services through standard EOL/PDN processes. Product certification and use condition information can be found in the Production Release Qualification (PRQ) report for this SKU. Contact your Intel representative for details.
Max Memory Size (dependent on memory type)
Max memory size refers to the maximum memory capacity supported by the processor.
Memory Types
Intel® processors come in four different types: Single Channel, Dual Channel, Triple Channel, and Flex Mode. Maximum supported memory speed may be lower when populating multiple DIMMs per channel on products that support multiple memory channels.
Max # of Memory Channels
The number of memory channels refers to the bandwidth operation for real world application.
Max Memory Bandwidth
Max Memory bandwidth is the maximum rate at which data can be read from or stored into a semiconductor memory by the processor (in GB/s).
ECC Memory Supported ‡
ECC Memory Supported indicates processor support for Error-Correcting Code memory. ECC memory is a type of system memory that can detect and correct common kinds of internal data corruption. Note that ECC memory support requires both processor and chipset support.
Integrated Graphics ‡
Integrated graphics allow for incredible visual quality, faster graphic performance and flexible display options without the need for a separate graphics card.
Graphics Output
Graphics Output defines the interfaces available to communicate with display devices.
PCI Express Revision
PCI Express Revision is the supported version of the PCI Express standard. Peripheral Component Interconnect Express (or PCIe) is a high-speed serial computer expansion bus standard for attaching hardware devices to a computer. The different PCI Express versions support different data rates.
PCI Express Configurations ‡
PCI Express (PCIe) Configurations describe the available PCIe lane configurations that can be used to link to PCIe devices.
Max # of PCI Express Lanes
A PCI Express (PCIe) lane consists of two differential signaling pairs, one for receiving data, one for transmitting data, and is the basic unit of the PCIe bus. Max # of PCI Express Lanes is the total number of supported lanes.
TCASE
Case Temperature is the maximum temperature allowed at the processor Integrated Heat Spreader (IHS).
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.
System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.