Mobile Intel® Celeron® Processor 750 MHz, 128K Cache, 100 MHz FSB
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Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Cores is a hardware term that describes the number of independent central processing units in a single computing component (die or chip).
Processor Base Frequency
Processor Base Frequency describes the rate at which the processor's transistors open and close. The processor base frequency is the operating point where TDP is defined. Frequency is typically measured in gigahertz (GHz), or billion cycles per second.
CPU Cache is an area of fast memory located on the processor. Intel® Smart Cache refers to the architecture that allows all cores to dynamically share access to the last level cache.
A bus is a subsystem that transfers data between computer components or between computers. Types include front-side bus (FSB), which carries data between the CPU and memory controller hub; direct media interface (DMI), which is a point-to-point interconnection between an Intel integrated memory controller and an Intel I/O controller hub on the computer’s motherboard; and Quick Path Interconnect (QPI), which is a point-to-point interconnect between the CPU and the integrated memory controller.
FSB parity provides error checking on data sent on the FSB (Front Side Bus).
Thermal Design Power (TDP) represents the average power, in watts, the processor dissipates when operating at Base Frequency with all cores active under an Intel-defined, high-complexity workload. Refer to Datasheet for thermal solution requirements.
VID Voltage Range
VID Voltage Range is an indicator of the minimum and maximum voltage values at which the processor is designed to operate. The processor communicates VID to the VRM (Voltage Regulator Module), which in turn delivers that correct voltage to the processor.
Embedded Options Available
Embedded Options Available indicates products that offer extended purchase availability for intelligent systems and embedded solutions. Product certification and use condition applications can be found in the Production Release Qualification (PRQ) report. See your Intel representative for details.
Physical Address Extensions
Physical Address Extensions (PAE) is a feature that allows 32-bit processors to access a physical address space larger than 4 gigabytes.
ECC Memory Supported ‡
ECC Memory Supported indicates processor support for Error-Correcting Code memory. ECC memory is a type of system memory that can detect and correct common kinds of internal data corruption. Note that ECC memory support requires both processor and chipset support.
The socket is the component that provides the mechanical and electrical connections between the processor and motherboard.
Junction Temperature is the maximum temperature allowed at the processor die.
Intel® Turbo Boost Technology ‡
Intel® Turbo Boost Technology dynamically increases the processor's frequency as needed by taking advantage of thermal and power headroom to give you a burst of speed when you need it, and increased energy efficiency when you don’t.
Intel® Hyper-Threading Technology ‡
Intel® Hyper-Threading Technology (Intel® HT Technology) delivers two processing threads per physical core. Highly threaded applications can get more work done in parallel, completing tasks sooner.
Intel® Virtualization Technology (VT-x) ‡
Intel® Virtualization Technology (VT-x) allows one hardware platform to function as multiple “virtual” platforms. It offers improved manageability by limiting downtime and maintaining productivity by isolating computing activities into separate partitions.
Intel® 64 ‡
Intel® 64 architecture delivers 64-bit computing on server, workstation, desktop and mobile platforms when combined with supporting software.¹ Intel 64 architecture improves performance by allowing systems to address more than 4 GB of both virtual and physical memory.
An instruction set refers to the basic set of commands and instructions that a microprocessor understands and can carry out. The value shown represents which Intel’s instruction set this processor is compatible with.
Idle States (C-states) are used to save power when the processor is idle. C0 is the operational state, meaning that the CPU is doing useful work. C1 is the first idle state, C2 the second, and so on, where more power saving actions are taken for numerically higher C-states.
Enhanced Intel SpeedStep® Technology
Enhanced Intel SpeedStep® Technology is an advanced means of enabling high performance while meeting the power-conservation needs of mobile systems. Conventional Intel SpeedStep® Technology switches both voltage and frequency in tandem between high and low levels in response to processor load. Enhanced Intel SpeedStep® Technology builds upon that architecture using design strategies such as Separation between Voltage and Frequency Changes, and Clock Partitioning and Recovery.
Intel® Demand Based Switching
Intel® Demand Based Switching is a power-management technology in which the applied voltage and clock speed of a microprocessor are kept at the minimum necessary levels until more processing power is required. This technology was introduced as Intel SpeedStep® Technology in the server marketplace.
Intel® Trusted Execution Technology ‡
Intel® Trusted Execution Technology for safer computing is a versatile set of hardware extensions to Intel® processors and chipsets that enhance the digital office platform with security capabilities such as measured launch and protected execution. It enables an environment where applications can run within their own space, protected from all other software on the system.
Execute Disable Bit ‡
Execute Disable Bit is a hardware-based security feature that can reduce exposure to viruses and malicious-code attacks and prevent harmful software from executing and propagating on the server or network.
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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for informational purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
See http://www.intel.com/content/www/us/en/architecture-and-technology/hyper-threading/hyper-threading-technology.html?wapkw=hyper+threading for more information including details on which processors support Intel® HT Technology.
Max Turbo Frequency refers to the maximum single-core processor frequency that can be achieved with Intel® Turbo Boost Technology. See www.intel.com/technology/turboboost/ for more information and applicability of this technology.
Processors that support 64-bit computing on Intel® architecture require an Intel 64 architecture-enabled BIOS.
System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.