Intel® Agilex™ 7 FPGA F-Series 012
Specifications
Compare Intel® Products
Essentials
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Product Collection
Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
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Marketing Status
Launched
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Launch Date
Q2'19
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Lithography
10 nm
Resources
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Logic Elements (LE)
1178525
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Adaptive Logic Modules (ALM)
399500
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Adaptive Logic Module (ALM) Registers
1598000
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Fabric and I/O Phase-Locked Loops (PLLs)
24
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Maximum Embedded Memory
163 Mb
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Digital Signal Processing (DSP) Blocks
3743
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Digital Signal Processing (DSP) Format
Fixed Point (hard IP), Floating Point (hard IP), Multiply, Multiply and Accumulate, Variable Precision
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Hard Processor System (HPS)
Quad-core 64 bit Arm* Cortex*-A53
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Hard Crypto Blocks
0
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, QDR IV
I/O Specifications
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Maximum User I/O Count†
744
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I/O Standards Support
1.2 V LVCMOS, 1.8 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, True Differential Signaling
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Maximum LVDS Pairs
372
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Maximum Non-Return to Zero (NRZ) Transceivers†
32
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Maximum Non-Return to Zero (NRZ) Data Rate†
32 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
24
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
58 Gbps
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Transceiver Protocol Hard IP
PCIe Gen4, 10/25/50/100/200/400G Ethernet
Advanced Technologies
Package Specifications
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Package Options
R2340A
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
Ordering and spec information
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFA012R24C2E2V
- MM# 99AZ30
- Spec Code SRLX9
- Ordering Code AGFA012R24C2E2V
- Stepping B2
- ECCN 3A001.A.7.A
- CCATS G171972
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFA012R24C2E3V
- MM# 99AZ35
- Spec Code SRLXA
- Ordering Code AGFA012R24C2E3V
- Stepping B2
- ECCN 3A001.A.7.A
- CCATS G171972
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFB012R24C2E2V
- MM# 99AZ76
- Spec Code SRLYN
- Ordering Code AGFB012R24C2E2V
- Stepping B2
- ECCN 5A002U
- CCATS G178951
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFB012R24C2E3V
- MM# 99AZ7L
- Spec Code SRLYQ
- Ordering Code AGFB012R24C2E3V
- Stepping B2
- ECCN 5A002U
- CCATS G178951
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFA012R24C2E1VB
- MM# 99CAJN
- Spec Code SRMSE
- Ordering Code AGFA012R24C2E1VB
- Stepping B2
- ECCN 3A001.A.7.A
- CCATS G171972
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFA012R24C2E2VB
- MM# 99CAJP
- Spec Code SRMSF
- Ordering Code AGFA012R24C2E2VB
- Stepping B2
- ECCN 3A001.A.7.A
- CCATS G171972
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFA012R24C2I1VB
- MM# 99CAJR
- Spec Code SRMSG
- Ordering Code AGFA012R24C2I1VB
- Stepping B2
- ECCN 3A001.A.7.A
- CCATS G171972
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFA012R24C2I2VB
- MM# 99CAJT
- Spec Code SRMSH
- Ordering Code AGFA012R24C2I2VB
- Stepping B2
- ECCN 3A001.A.7.A
- CCATS G171972
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFB012R24C2E1VB
- MM# 99CAMD
- Spec Code SRMU2
- Ordering Code AGFB012R24C2E1VB
- Stepping B2
- ECCN 5A002U
- CCATS G178951
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFB012R24C2E2VB
- MM# 99CAMF
- Spec Code SRMU3
- Ordering Code AGFB012R24C2E2VB
- Stepping B2
- ECCN 5A002U
- CCATS G178951
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFB012R24C2I1VB
- MM# 99CAMG
- Spec Code SRMU4
- Ordering Code AGFB012R24C2I1VB
- Stepping B2
- ECCN 5A002U
- CCATS G178951
Intel® Agilex™ 7 FPGA F-Series 012 (R24C) AGFB012R24C2I2VB
- MM# 99CAMH
- Spec Code SRMU5
- Ordering Code AGFB012R24C2I2VB
- Stepping B2
- ECCN 5A002U
- CCATS G178951
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SRLXC
- 99AZ37 PCN
SRLXD
- 99AZ3C PCN
SRLXE
- 99AZ3D PCN
SRLXF
- 99AZ3H PCN
SRM6X
- 99C244 PCN
SRLXA
- 99AZ35 PCN
SRLXB
- 99AZ36 PCN
SRLX8
- 99AZ2Z PCN
SRLX9
- 99AZ30 PCN
SRM6V
- 99C242 PCN
SRLYN
- 99AZ76 PCN
SRLYP
- 99AZ7C PCN
SRLYQ
- 99AZ7L PCN
SRLYR
- 99AZ7M PCN
SRLYD
- 99AZ6P PCN
SRLYE
- 99AZ6T PCN
SRLYF
- 99AZ6V PCN
SRLYG
- 99AZ6X PCN
SRLYH
- 99AZ6Z PCN
SRLXS
- 99AZ55 PCN
SRLY4
- 99AZ61 PCN
SRLY5
- 99AZ64 PCN
SRLXW
- 99AZ5L PCN
SRLY8
- 99AZ67 PCN
SRLXX
- 99AZ5M PCN
SRLXY
- 99AZ5N PCN
SRLXL
- 99AZ42 PCN
SRLY0
- 99AZ5W PCN
SRLY1
- 99AZ5X PCN
SRLXR
- 99AZ53 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
Give Feedback
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.