Intel Agilex® 7 FPGA I-Series 027

R31B

Specifications

Resources

I/O Specifications

Advanced Technologies

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1E1V

  • MM# 99AVZH
  • Spec Code SRLEC
  • Ordering Code AGIB027R31B1E1V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1E2V

  • MM# 99AVZX
  • Spec Code SRLED
  • Ordering Code AGIB027R31B1E2V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1I1V

  • MM# 99AW08
  • Spec Code SRLEE
  • Ordering Code AGIB027R31B1I1V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1I2V

  • MM# 99AW09
  • Spec Code SRLEF
  • Ordering Code AGIB027R31B1I2V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E1V

  • MM# 99AW0A
  • Spec Code SRLEG
  • Ordering Code AGIB027R31B2E1V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E2V

  • MM# 99AW0C
  • Spec Code SRLEH
  • Ordering Code AGIB027R31B2E2V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E3V

  • MM# 99AW0D
  • Spec Code SRLEJ
  • Ordering Code AGIB027R31B2E3V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I1V

  • MM# 99AW0F
  • Spec Code SRLEK
  • Ordering Code AGIB027R31B2I1V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I2V

  • MM# 99AW0G
  • Spec Code SRLEL
  • Ordering Code AGIB027R31B2I2V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I3V

  • MM# 99AW0H
  • Spec Code SRLEM
  • Ordering Code AGIB027R31B2I3V
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B3E3E

  • MM# 99AW0J
  • Spec Code SRLEN
  • Ordering Code AGIB027R31B3E3E
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B3I3E

  • MM# 99AW0K
  • Spec Code SRLEP
  • Ordering Code AGIB027R31B3I3E
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E3E

  • MM# 99AW0L
  • Spec Code SRLEQ
  • Ordering Code AGIB027R31B2E3E
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I3E

  • MM# 99AW0M
  • Spec Code SRLER
  • Ordering Code AGIB027R31B2I3E
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1E1VAA

  • MM# 99C45Z
  • Spec Code SRMAM
  • Ordering Code AGIB027R31B1E1VAA
  • Stepping A5
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1E1VB

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E1VB

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1E2VB

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E2VB

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1I1VB

  • MM# 99C7TK
  • Spec Code SRMKC
  • Ordering Code AGIB027R31B1I1VB
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I1VB

  • MM# 99C7TR
  • Spec Code SRMKD
  • Ordering Code AGIB027R31B2I1VB
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1I2VB

  • MM# 99C7TT
  • Spec Code SRMKE
  • Ordering Code AGIB027R31B1I2VB
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I2VB

  • MM# 99C7TV
  • Spec Code SRMKF
  • Ordering Code AGIB027R31B2I2VB
  • Stepping A4
  • MDDS Content IDs 785402

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1E2VC

  • MM# 99CHDH
  • Spec Code SRNKC
  • Ordering Code AGIB027R31B1E2VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I1VC

  • MM# 99CHFN
  • Spec Code SRNLF
  • Ordering Code AGIB027R31B2I1VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E1VC

  • MM# 99CHG1
  • Spec Code SRNLQ
  • Ordering Code AGIB027R31B2E1VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I3VC

  • MM# 99CHJ7
  • Spec Code SRNNS
  • Ordering Code AGIB027R31B2I3VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1I1VC

  • MM# 99CHJG
  • Spec Code SRNNZ
  • Ordering Code AGIB027R31B1I1VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1I2VC

  • MM# 99CHK0
  • Spec Code SRNPH
  • Ordering Code AGIB027R31B1I2VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I3EC

  • MM# 99CHLX
  • Spec Code SRNRA
  • Ordering Code AGIB027R31B2I3EC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E2VC

  • MM# 99CHRF
  • Spec Code SRNUK
  • Ordering Code AGIB027R31B2E2VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E3VC

  • MM# 99CHW0
  • Spec Code SRNWW
  • Ordering Code AGIB027R31B2E3VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B1E1VC

  • MM# 99CHXT
  • Spec Code SRNYM
  • Ordering Code AGIB027R31B1E1VC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2E3EC

  • MM# 99CJ0W
  • Spec Code SRP2K
  • Ordering Code AGIB027R31B2E3EC
  • Stepping A2

Intel Agilex® 7 FPGA I-Series 027 (R31B) AGIB027R31B2I2VC

  • MM# 99CJ49
  • Spec Code SRP5R
  • Ordering Code AGIB027R31B2I2VC
  • Stepping A2

Trade compliance information

  • ECCN 5A002U
  • CCATS G178951
  • US HTS 8542390001

PCN Information

SRLEP

SRLEQ

SRLER

SRMAM

SRMK8

SRMK9

SRLEH

SRLEJ

SRLEK

SRLEL

SRLEM

SRLEN

SRMKE

SRMKF

SRLEC

SRLED

SRLEE

SRLEF

SRLEG

SRMKA

SRMKB

SRMKC

SRMKD

Drivers and Software

Latest Drivers & Software

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Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Maximum Pulse-Amplitude Modulation (PAM4) Transceivers

The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Pulse-Amplitude Modulation (PAM4) Data Rate

The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.