Cyclone® IV EP4CGX150 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF27I7

  • MM# 967080
  • Spec Code SR5XV
  • Ordering Code EP4CGX150DF27I7
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150CF23C7

  • MM# 967330
  • Spec Code SR64V
  • Ordering Code EP4CGX150CF23C7
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150CF23I7N

  • MM# 967331
  • Spec Code SR64W
  • Ordering Code EP4CGX150CF23I7N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF31C7N

  • MM# 967332
  • Spec Code SR64X
  • Ordering Code EP4CGX150DF31C7N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF31C8

  • MM# 967333
  • Spec Code SR64Y
  • Ordering Code EP4CGX150DF31C8
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF31C8N

  • MM# 970235
  • Spec Code SR8JB
  • Ordering Code EP4CGX150DF31C8N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF31I7

  • MM# 970236
  • Spec Code SR8JC
  • Ordering Code EP4CGX150DF31I7
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF27C7

  • MM# 971177
  • Spec Code SR9DL
  • Ordering Code EP4CGX150DF27C7
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF27C8N

  • MM# 971924
  • Spec Code SRAHM
  • Ordering Code EP4CGX150DF27C8N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF31C7

  • MM# 971925
  • Spec Code SRAHN
  • Ordering Code EP4CGX150DF31C7
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF31I7N

  • MM# 971926
  • Spec Code SRAHP
  • Ordering Code EP4CGX150DF31I7N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150CF23C7N

  • MM# 972538
  • Spec Code SRAN1
  • Ordering Code EP4CGX150CF23C7N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150CF23C8

  • MM# 972539
  • Spec Code SRAN2
  • Ordering Code EP4CGX150CF23C8
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150CF23C8N

  • MM# 972540
  • Spec Code SRAN3
  • Ordering Code EP4CGX150CF23C8N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF27C7N

  • MM# 972678
  • Spec Code SRAS5
  • Ordering Code EP4CGX150DF27C7N
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF27C8

  • MM# 972679
  • Spec Code SRAS6
  • Ordering Code EP4CGX150DF27C8
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150CF23I7

  • MM# 973214
  • Spec Code SRB5Q
  • Ordering Code EP4CGX150CF23I7
  • Stepping A1

Cyclone® IV EP4CGX150 FPGA EP4CGX150DF27I7N

  • MM# 974437
  • Spec Code SRCH2
  • Ordering Code EP4CGX150DF27I7N
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR5XV

SR8JC

SR8JB

SRB5Q

SR64Y

SR64X

SR64W

SR64V

SRAHM

SRAN3

SRAN2

SRAN1

SRAS6

SRAS5

SR9DL

SRCH2

SRAHP

SRAHN

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.