Cyclone® IV EP4CGX110 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® IV EP4CGX110 FPGA EP4CGX110CF23C8N

  • MM# 967069
  • Spec Code SR5XJ
  • Ordering Code EP4CGX110CF23C8N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110CF23I7

  • MM# 967077
  • Spec Code SR5XS
  • Ordering Code EP4CGX110CF23I7
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF31I7

  • MM# 967078
  • Spec Code SR5XT
  • Ordering Code EP4CGX110DF31I7
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF27C8N

  • MM# 967328
  • Spec Code SR64T
  • Ordering Code EP4CGX110DF27C8N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF31C8N

  • MM# 967329
  • Spec Code SR64U
  • Ordering Code EP4CGX110DF31C8N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110CF23C7N

  • MM# 970233
  • Spec Code SR8J9
  • Ordering Code EP4CGX110CF23C7N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF27I7

  • MM# 970234
  • Spec Code SR8JA
  • Ordering Code EP4CGX110DF27I7
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF27C8

  • MM# 971175
  • Spec Code SR9DJ
  • Ordering Code EP4CGX110DF27C8
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF31I7N

  • MM# 971176
  • Spec Code SR9DK
  • Ordering Code EP4CGX110DF31I7N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110CF23I7N

  • MM# 971920
  • Spec Code SRAHH
  • Ordering Code EP4CGX110CF23I7N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF27C7

  • MM# 971921
  • Spec Code SRAHJ
  • Ordering Code EP4CGX110DF27C7
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF27I7N

  • MM# 971922
  • Spec Code SRAHK
  • Ordering Code EP4CGX110DF27I7N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF31C7N

  • MM# 971923
  • Spec Code SRAHL
  • Ordering Code EP4CGX110DF31C7N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110CF23C8

  • MM# 972537
  • Spec Code SRAN0
  • Ordering Code EP4CGX110CF23C8
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF27C7N

  • MM# 973212
  • Spec Code SRB5N
  • Ordering Code EP4CGX110DF27C7N
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF31C7

  • MM# 973213
  • Spec Code SRB5P
  • Ordering Code EP4CGX110DF31C7
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110CF23C7

  • MM# 974435
  • Spec Code SRCH0
  • Ordering Code EP4CGX110CF23C7
  • Stepping A1

Cyclone® IV EP4CGX110 FPGA EP4CGX110DF31C8

  • MM# 974436
  • Spec Code SRCH1
  • Ordering Code EP4CGX110DF31C8
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR64T

SR5XT

SR5XS

SR8JA

SRB5P

SRB5N

SR64U

SRAHL

SRAHK

SRAHJ

SRAN0

SRAHH

SR9DK

SR9DJ

SRCH1

SRCH0

SR5XJ

SR8J9

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.