Cyclone® IV EP4CGX22 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14C7N

  • MM# 967174
  • Spec Code SR609
  • Ordering Code EP4CGX22BF14C7N
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14C8

  • MM# 967175
  • Spec Code SR60A
  • Ordering Code EP4CGX22BF14C8
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19C8

  • MM# 967177
  • Spec Code SR60C
  • Ordering Code EP4CGX22CF19C8
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19I7N

  • MM# 967178
  • Spec Code SR60D
  • Ordering Code EP4CGX22CF19I7N
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14C6N

  • MM# 970238
  • Spec Code SR8JE
  • Ordering Code EP4CGX22BF14C6N
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14C7

  • MM# 970239
  • Spec Code SR8JF
  • Ordering Code EP4CGX22BF14C7
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19C6N

  • MM# 970240
  • Spec Code SR8JG
  • Ordering Code EP4CGX22CF19C6N
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19C7

  • MM# 970241
  • Spec Code SR8JH
  • Ordering Code EP4CGX22CF19C7
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19I7

  • MM# 970242
  • Spec Code SR8JJ
  • Ordering Code EP4CGX22CF19I7
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14C6

  • MM# 971930
  • Spec Code SRAHT
  • Ordering Code EP4CGX22BF14C6
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14C8N

  • MM# 972682
  • Spec Code SRAS9
  • Ordering Code EP4CGX22BF14C8N
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14I7

  • MM# 973215
  • Spec Code SRB5R
  • Ordering Code EP4CGX22BF14I7
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19C6

  • MM# 973216
  • Spec Code SRB5S
  • Ordering Code EP4CGX22CF19C6
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19C8N

  • MM# 973217
  • Spec Code SRB5T
  • Ordering Code EP4CGX22CF19C8N
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22BF14I7N

  • MM# 974439
  • Spec Code SRCH4
  • Ordering Code EP4CGX22BF14I7N
  • Stepping A1

Cyclone® IV EP4CGX22 FPGA EP4CGX22CF19C7N

  • MM# 974440
  • Spec Code SRCH5
  • Ordering Code EP4CGX22CF19C7N
  • Stepping A1

Trade compliance information

  • ECCN EAR99
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR8JH

SR8JG

SR8JF

SR8JE

SRCH5

SRCH4

SR8JJ

SRB5T

SRB5S

SR609

SRB5R

SRAHT

SR60D

SR60C

SR60A

SRAS9

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.