Cyclone® IV EP4CE30 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® IV EP4CE30 FPGA EP4CE30F29C8N

  • MM# 967035
  • Spec Code SR5WJ
  • Ordering Code EP4CE30F29C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29I8L

  • MM# 967036
  • Spec Code SR5WK
  • Ordering Code EP4CE30F29I8L
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23A7N

  • MM# 967305
  • Spec Code SR644
  • Ordering Code EP4CE30F23A7N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C8L

  • MM# 967306
  • Spec Code SR645
  • Ordering Code EP4CE30F23C8L
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23I7N

  • MM# 967307
  • Spec Code SR646
  • Ordering Code EP4CE30F23I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23I8LN

  • MM# 967308
  • Spec Code SR647
  • Ordering Code EP4CE30F23I8LN
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C8L

  • MM# 967309
  • Spec Code SR648
  • Ordering Code EP4CE30F29C8L
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C7N

  • MM# 970214
  • Spec Code SR8HQ
  • Ordering Code EP4CE30F29C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C7

  • MM# 971159
  • Spec Code SR9D2
  • Ordering Code EP4CE30F29C7
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C9L

  • MM# 971160
  • Spec Code SR9D3
  • Ordering Code EP4CE30F29C9L
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29I7

  • MM# 971161
  • Spec Code SR9D4
  • Ordering Code EP4CE30F29I7
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29I7N

  • MM# 971162
  • Spec Code SR9D5
  • Ordering Code EP4CE30F29I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29I8LN

  • MM# 971163
  • Spec Code SR9D6
  • Ordering Code EP4CE30F29I8LN
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F19A7N

  • MM# 971891
  • Spec Code SRAGN
  • Ordering Code EP4CE30F19A7N
  • Stepping A1
  • ECCN EAR99

Cyclone® IV EP4CE30 FPGA EP4CE30F23C6N

  • MM# 971892
  • Spec Code SRAGP
  • Ordering Code EP4CE30F23C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C8LN

  • MM# 971893
  • Spec Code SRAGQ
  • Ordering Code EP4CE30F23C8LN
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23I7

  • MM# 971894
  • Spec Code SRAGR
  • Ordering Code EP4CE30F23I7
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C8LN

  • MM# 971895
  • Spec Code SRAGS
  • Ordering Code EP4CE30F29C8LN
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C6

  • MM# 972519
  • Spec Code SRAMG
  • Ordering Code EP4CE30F23C6
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C7

  • MM# 972520
  • Spec Code SRAMH
  • Ordering Code EP4CE30F23C7
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C7N

  • MM# 972521
  • Spec Code SRAMJ
  • Ordering Code EP4CE30F23C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C6N

  • MM# 972522
  • Spec Code SRAMK
  • Ordering Code EP4CE30F29C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C8

  • MM# 973190
  • Spec Code SRB50
  • Ordering Code EP4CE30F23C8
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C8N

  • MM# 973191
  • Spec Code SRB51
  • Ordering Code EP4CE30F23C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C9L

  • MM# 973192
  • Spec Code SRB52
  • Ordering Code EP4CE30F23C9L
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23C9LN

  • MM# 973193
  • Spec Code SRB53
  • Ordering Code EP4CE30F23C9LN
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C6

  • MM# 973194
  • Spec Code SRB54
  • Ordering Code EP4CE30F29C6
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C8

  • MM# 973195
  • Spec Code SRB55
  • Ordering Code EP4CE30F29C8
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F29C9LN

  • MM# 973196
  • Spec Code SRB56
  • Ordering Code EP4CE30F29C9LN
  • Stepping A1
  • ECCN 3A991

Cyclone® IV EP4CE30 FPGA EP4CE30F23I8L

  • MM# 974418
  • Spec Code SRCGH
  • Ordering Code EP4CE30F23I8L
  • Stepping A1
  • ECCN 3A991

Trade compliance information

  • ECCN Varies By Product
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR644

SR648

SR647

SR646

SR645

SRCGH

SRB56

SRB55

SRB54

SRB53

SRAMK

SRB52

SRAGS

SRAGR

SR9D6

SRAGQ

SR9D5

SRAGP

SR9D4

SR9D3

SRAGN

SR9D2

SRAMJ

SRB51

SRB50

SRAMH

SRAMG

SR8HQ

SR5WK

SR5WJ

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.