Cyclone® IV EP4CE40 FPGA
Specifications
Compare Intel® Products
Essentials
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Product Collection
Cyclone® IV E FPGA
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Marketing Status
Launched
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Launch Date
2009
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Lithography
60 nm
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Resources
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Logic Elements (LE)
40000
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Fabric and I/O Phase-Locked Loops (PLLs)
4
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Maximum Embedded Memory
1.134 Mb
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Digital Signal Processing (DSP) Blocks
116
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Digital Signal Processing (DSP) Format
Multiply
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Hard Memory Controllers
No
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External Memory Interfaces (EMIF)
DDR, DDR2, SDR
I/O Specifications
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Maximum User I/O Count†
532
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3 V LVCMOS, PCI, PCI-X, SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS, PPDS
Advanced Technologies
Package Specifications
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Package Options
U484, F324, F484, F780
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Cyclone IV Featured Documentation
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Cyclone® IV EP4CE40 FPGA EP4CE40U19I7
- MM# 974422
- Spec Code SRCGM
- Ordering Code EP4CE40U19I7
- Stepping A1
- ECCN 3A991
Trade compliance information
- ECCN Varies By Product
- CCATS NA
- US HTS 8542390001
PCN Information
SRAGZ
- 971902 PCN
SRAGY
- 971901 PCN
SRAGX
- 971900 PCN
SRAGW
- 971899 PCN
SRAGV
- 971898 PCN
SRAGU
- 971897 PCN
SRB5B
- 973201 PCN
SR649
- 967310 PCN
SRB59
- 973199 PCN
SRCGJ
- 974419 PCN
SRB58
- 973198 PCN
SRB57
- 973197 PCN
SRAMM
- 972524 PCN
SRAML
- 972523 PCN
SR9D9
- 971166 PCN
SRAGT
- 971896 PCN
SRB5A
- 973200 PCN
SR9D8
- 971165 PCN
SR9D7
- 971164 PCN
SRCGM
- 974422 PCN
SRCGL
- 974421 PCN
SRCGK
- 974420 PCN
SR5WQ
- 967041 PCN
SR8HV
- 970219 PCN
SR8HU
- 970218 PCN
SR64B
- 967312 PCN
SR8HT
- 970217 PCN
SR64A
- 967311 PCN
SR8HS
- 970216 PCN
SR8HR
- 970215 PCN
SR5WP
- 967040 PCN
SR5WN
- 967039 PCN
SR5WM
- 967038 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Analog-to-Digital Converter
The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.