Cyclone® IV EP4CE115 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® IV EP4CE115 FPGA EP4CE115F23C8

  • MM# 967019
  • Spec Code SR5W2
  • Ordering Code EP4CE115F23C8
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C8N

  • MM# 967020
  • Spec Code SR5W3
  • Ordering Code EP4CE115F29C8N
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C9L

  • MM# 967021
  • Spec Code SR5W4
  • Ordering Code EP4CE115F29C9L
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C9LN

  • MM# 967022
  • Spec Code SR5W5
  • Ordering Code EP4CE115F29C9LN
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29I8L

  • MM# 967023
  • Spec Code SR5W6
  • Ordering Code EP4CE115F29I8L
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F23C8L

  • MM# 967287
  • Spec Code SR63L
  • Ordering Code EP4CE115F23C8L
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F23C9L

  • MM# 967288
  • Spec Code SR63M
  • Ordering Code EP4CE115F23C9L
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29I7N

  • MM# 970202
  • Spec Code SR8HC
  • Ordering Code EP4CE115F29I7N
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29I8LN

  • MM# 970203
  • Spec Code SR8HD
  • Ordering Code EP4CE115F29I8LN
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F23I7

  • MM# 971150
  • Spec Code SR9CT
  • Ordering Code EP4CE115F23I7
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F23C7

  • MM# 971883
  • Spec Code SRAGE
  • Ordering Code EP4CE115F23C7
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C8

  • MM# 972463
  • Spec Code SRA2H
  • Ordering Code EP4CE115F29C8
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F23I8L

  • MM# 973172
  • Spec Code SRB4G
  • Ordering Code EP4CE115F23I8L
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C7

  • MM# 973173
  • Spec Code SRB4H
  • Ordering Code EP4CE115F29C7
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C7N

  • MM# 973174
  • Spec Code SRB4J
  • Ordering Code EP4CE115F29C7N
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C8L

  • MM# 973176
  • Spec Code SRB4L
  • Ordering Code EP4CE115F29C8L
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29C8LN

  • MM# 973177
  • Spec Code SRB4M
  • Ordering Code EP4CE115F29C8LN
  • Stepping A1

Cyclone® IV EP4CE115 FPGA EP4CE115F29I7

  • MM# 973178
  • Spec Code SRB4N
  • Ordering Code EP4CE115F29I7
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SRB4H

SRB4G

SR5W6

SR8HD

SR5W5

SR8HC

SR5W4

SR5W3

SR5W2

SR63M

SR63L

SRB4N

SRB4M

SRB4L

SRB4J

SRA2H

SRAGE

SR9CT

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.