Cyclone® IV EP4CE10 FPGA


I/O Specifications

Package Specifications

Ordering and Compliance

Ordering and spec information

Cyclone® IV EP4CE10 FPGA EP4CE10F17C8

  • MM# 967285
  • Spec Code SR63J
  • Ordering Code EP4CE10F17C8
  • Stepping A1
  • MDDS Content IDs 699777

Cyclone® IV EP4CE10 FPGA EP4CE10F17C9LN

  • MM# 967286
  • Spec Code SR63K
  • Ordering Code EP4CE10F17C9LN
  • Stepping A1
  • MDDS Content IDs 699067

Cyclone® IV EP4CE10 FPGA EP4CE10F17C6N

  • MM# 970201
  • Spec Code SR8HB
  • Ordering Code EP4CE10F17C6N
  • Stepping A1
  • MDDS Content IDs 693286744318

Cyclone® IV EP4CE10 FPGA EP4CE10F17C6

  • MM# 971147
  • Spec Code SR9CQ
  • Ordering Code EP4CE10F17C6
  • Stepping A1
  • MDDS Content IDs 701917

Cyclone® IV EP4CE10 FPGA EP4CE10F17I8LN

  • MM# 971148
  • Spec Code SR9CR
  • Ordering Code EP4CE10F17I8LN
  • Stepping A1
  • MDDS Content IDs 691997746541

Cyclone® IV EP4CE10 FPGA EP4CE10U14I7N

  • MM# 971149
  • Spec Code SR9CS
  • Ordering Code EP4CE10U14I7N
  • Stepping A1
  • MDDS Content IDs 695321746599

Cyclone® IV EP4CE10 FPGA EP4CE10F17C7

  • MM# 971879
  • Spec Code SRAGA
  • Ordering Code EP4CE10F17C7
  • Stepping A1
  • MDDS Content IDs 699255

Cyclone® IV EP4CE10 FPGA EP4CE10F17C8LN

  • MM# 971880
  • Spec Code SRAGB
  • Ordering Code EP4CE10F17C8LN
  • Stepping A1
  • MDDS Content IDs 697662

Cyclone® IV EP4CE10 FPGA EP4CE10F17C9L

  • MM# 971881
  • Spec Code SRAGC
  • Ordering Code EP4CE10F17C9L
  • Stepping A1
  • MDDS Content IDs 694062

Cyclone® IV EP4CE10 FPGA EP4CE10F17I7

  • MM# 971882
  • Spec Code SRAGD
  • Ordering Code EP4CE10F17I7
  • Stepping A1
  • MDDS Content IDs 700449

Cyclone® IV EP4CE10 FPGA EP4CE10F17C7N

  • MM# 972459
  • Spec Code SRA2D
  • Ordering Code EP4CE10F17C7N
  • Stepping A1
  • MDDS Content IDs 701381745970

Cyclone® IV EP4CE10 FPGA EP4CE10F17C8L

  • MM# 972460
  • Spec Code SRA2E
  • Ordering Code EP4CE10F17C8L
  • Stepping A1
  • MDDS Content IDs 701573

Cyclone® IV EP4CE10 FPGA EP4CE10F17I8L

  • MM# 972461
  • Spec Code SRA2F
  • Ordering Code EP4CE10F17I8L
  • Stepping A1
  • MDDS Content IDs 699226

Cyclone® IV EP4CE10 FPGA EP4CE10F17C8N

  • MM# 973169
  • Spec Code SRB4D
  • Ordering Code EP4CE10F17C8N
  • Stepping A1
  • MDDS Content IDs 700128746218

Cyclone® IV EP4CE10 FPGA EP4CE10F17A7N

  • MM# 974402
  • Spec Code SRCG1
  • Ordering Code EP4CE10F17A7N
  • Stepping A1
  • MDDS Content IDs 691620744621

Cyclone® IV EP4CE10 FPGA EP4CE10F17I7N

  • MM# 974403
  • Spec Code SRCG2
  • Ordering Code EP4CE10F17I7N
  • Stepping A1
  • MDDS Content IDs 699134745513

Trade compliance information

  • ECCN EAR99
  • US HTS 8542390001

PCN Information

















Drivers and Software

Latest Drivers & Software

Downloads Available:


Launch Date

The date the product was first introduced.


Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.