
Cyclone® V 5CSEA5 FPGA
Specifications
Compare Intel® Products
Essentials
-
Product Collection
Cyclone® V SE SoC FPGA
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Status
Launched
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Launch Date
2012
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Lithography
28 nm
Resources
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Logic Elements (LE)
85000
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Adaptive Logic Modules (ALM)
32075
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Adaptive Logic Module (ALM) Registers
128300
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Fabric and I/O Phase-Locked Loops (PLLs)
6
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Maximum Embedded Memory
4.45 Mb
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Digital Signal Processing (DSP) Blocks
87
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Digital Signal Processing (DSP) Format
Variable Precision
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Hard Processor System (HPS)
Single Arm* Cortex*-A9 or Dual-core Arm* Cortex*-A9
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR2, DDR3, LPDDR2
I/O Specifications
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Maximum User I/O Count†
288
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3 V LVCMOS, PCI, PCI-X, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, HiSpi, SLVS, Sub-LVDS
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Maximum LVDS Pairs
144
Advanced Technologies
Package Specifications
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Package Options
U484, U672, F896
Supplemental Information
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Additional Information
View now
Ordering and Compliance
Ordering and spec information
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C6N
- MM# 965719
- Spec Code SR4SL
- Ordering Code 5CSEBA5U19C6N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEMA5F31A7N
- MM# 965723
- Spec Code SR4SQ
- Ordering Code 5CSEMA5F31A7N
- Stepping A1
- ECCN 3A991
Cyclone® V 5CSEA5 FPGA 5CSEMA5F31C7N
- MM# 965724
- Spec Code SR4SR
- Ordering Code 5CSEMA5F31C7N
- Stepping A1
- ECCN 3A991
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19A7N
- MM# 965989
- Spec Code SR50F
- Ordering Code 5CSEBA5U19A7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C7N
- MM# 965990
- Spec Code SR50G
- Ordering Code 5CSEBA5U23C7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23I7SN
- MM# 965991
- Spec Code SR50H
- Ordering Code 5CSEBA5U23I7SN
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEMA5U23A7N
- MM# 966134
- Spec Code SR54Q
- Ordering Code 5CSEMA5U23A7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C7N
- MM# 968242
- Spec Code SR6WV
- Ordering Code 5CSEBA5U19C7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19I7SN
- MM# 968243
- Spec Code SR6WW
- Ordering Code 5CSEBA5U19I7SN
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEMA5F31C8N
- MM# 968247
- Spec Code SR6X0
- Ordering Code 5CSEMA5F31C8N
- Stepping A1
- ECCN 3A991
Cyclone® V 5CSEA5 FPGA 5CSEMA5U23I7N
- MM# 968249
- Spec Code SR6X2
- Ordering Code 5CSEMA5U23I7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19I7N
- MM# 968377
- Spec Code SR70N
- Ordering Code 5CSEBA5U19I7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C7SN
- MM# 968378
- Spec Code SR70P
- Ordering Code 5CSEBA5U23C7SN
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23I7
- MM# 968379
- Spec Code SR70Q
- Ordering Code 5CSEBA5U23I7
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEMA5F31I7N
- MM# 968382
- Spec Code SR70T
- Ordering Code 5CSEMA5F31I7N
- Stepping A1
- ECCN 3A991
Cyclone® V 5CSEA5 FPGA 5CSEMA5U23C6N
- MM# 968383
- Spec Code SR70U
- Ordering Code 5CSEMA5U23C6N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C8SN
- MM# 968977
- Spec Code SR7J5
- Ordering Code 5CSEBA5U19C8SN
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C8SN
- MM# 968979
- Spec Code SR7J7
- Ordering Code 5CSEBA5U23C8SN
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEMA5U23C7N
- MM# 969099
- Spec Code SR7MQ
- Ordering Code 5CSEMA5U23C7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C7SN
- MM# 969108
- Spec Code SR7N1
- Ordering Code 5CSEBA5U19C7SN
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23I7N
- MM# 969110
- Spec Code SR7N3
- Ordering Code 5CSEBA5U23I7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C8N
- MM# 969111
- Spec Code SR7N2
- Ordering Code 5CSEBA5U23C8N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEMA5F31C6N
- MM# 969117
- Spec Code SR7NA
- Ordering Code 5CSEMA5F31C6N
- Stepping A1
- ECCN 3A991
Cyclone® V 5CSEA5 FPGA 5CSEMA5U23C8N
- MM# 969119
- Spec Code SR7NC
- Ordering Code 5CSEMA5U23C8N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23A7N
- MM# 970635
- Spec Code SR8VG
- Ordering Code 5CSEBA5U23A7N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C8N
- MM# 973776
- Spec Code SRBN5
- Ordering Code 5CSEBA5U19C8N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C6N
- MM# 973778
- Spec Code SRBN7
- Ordering Code 5CSEBA5U23C6N
- Stepping A1
- ECCN EAR99
Cyclone® V 5CSEA5 FPGA 5CSEBA5U19I7LN
- MM# 999LG8
- Spec Code SRGN9
- Ordering Code 5CSEBA5U19I7LN
- Stepping A1
- ECCN EAR99
Trade compliance information
- ECCN Varies By Product
- CCATS NA
- US HTS 8542390001
PCN/MDDS Information
SRGN9
- 999LG8 PCN
SR7J7
- 968979 PCN
SR7J5
- 968977 PCN
SR7NC
- 969119 PCN
SRBN7
- 973778 PCN
SR7NA
- 969117 PCN
SR8VG
- 970635 PCN
SRBN5
- 973776 PCN
SR6WW
- 968243 PCN
SR6WV
- 968242 PCN
SR70N
- 968377 PCN
SR4SR
- 965724 PCN
SR4SQ
- 965723 PCN
SR54Q
- 966134 PCN
SR6X2
- 968249 PCN
SR70U
- 968383 PCN
SR7N3
- 969110 PCN
SR70T
- 968382 PCN
SR7MQ
- 969099 PCN
SR7N2
- 969111 PCN
SR7N1
- 969108 PCN
SR70Q
- 968379 PCN
SR70P
- 968378 PCN
SR6X0
- 968247 PCN
SR4SL
- 965719 PCN
SR50H
- 965991 PCN
SR50G
- 965990 PCN
SR50F
- 965989 PCN
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Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Analog-to-Digital Converter
The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
Give Feedback
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for informational purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.