Cyclone® V 5CSEA5 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C6N

  • MM# 965719
  • Spec Code SR4SL
  • Ordering Code 5CSEBA5U19C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEMA5F31A7N

  • MM# 965723
  • Spec Code SR4SQ
  • Ordering Code 5CSEMA5F31A7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CSEA5 FPGA 5CSEMA5F31C7N

  • MM# 965724
  • Spec Code SR4SR
  • Ordering Code 5CSEMA5F31C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19A7N

  • MM# 965989
  • Spec Code SR50F
  • Ordering Code 5CSEBA5U19A7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C7N

  • MM# 965990
  • Spec Code SR50G
  • Ordering Code 5CSEBA5U23C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23I7SN

  • MM# 965991
  • Spec Code SR50H
  • Ordering Code 5CSEBA5U23I7SN
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEMA5U23A7N

  • MM# 966134
  • Spec Code SR54Q
  • Ordering Code 5CSEMA5U23A7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C7N

  • MM# 968242
  • Spec Code SR6WV
  • Ordering Code 5CSEBA5U19C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19I7SN

  • MM# 968243
  • Spec Code SR6WW
  • Ordering Code 5CSEBA5U19I7SN
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEMA5F31C8N

  • MM# 968247
  • Spec Code SR6X0
  • Ordering Code 5CSEMA5F31C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CSEA5 FPGA 5CSEMA5U23I7N

  • MM# 968249
  • Spec Code SR6X2
  • Ordering Code 5CSEMA5U23I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19I7N

  • MM# 968377
  • Spec Code SR70N
  • Ordering Code 5CSEBA5U19I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C7SN

  • MM# 968378
  • Spec Code SR70P
  • Ordering Code 5CSEBA5U23C7SN
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23I7

  • MM# 968379
  • Spec Code SR70Q
  • Ordering Code 5CSEBA5U23I7
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEMA5F31I7N

  • MM# 968382
  • Spec Code SR70T
  • Ordering Code 5CSEMA5F31I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CSEA5 FPGA 5CSEMA5U23C6N

  • MM# 968383
  • Spec Code SR70U
  • Ordering Code 5CSEMA5U23C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C8SN

  • MM# 968977
  • Spec Code SR7J5
  • Ordering Code 5CSEBA5U19C8SN
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C8SN

  • MM# 968979
  • Spec Code SR7J7
  • Ordering Code 5CSEBA5U23C8SN
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEMA5U23C7N

  • MM# 969099
  • Spec Code SR7MQ
  • Ordering Code 5CSEMA5U23C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C7SN

  • MM# 969108
  • Spec Code SR7N1
  • Ordering Code 5CSEBA5U19C7SN
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23I7N

  • MM# 969110
  • Spec Code SR7N3
  • Ordering Code 5CSEBA5U23I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C8N

  • MM# 969111
  • Spec Code SR7N2
  • Ordering Code 5CSEBA5U23C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEMA5F31C6N

  • MM# 969117
  • Spec Code SR7NA
  • Ordering Code 5CSEMA5F31C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CSEA5 FPGA 5CSEMA5U23C8N

  • MM# 969119
  • Spec Code SR7NC
  • Ordering Code 5CSEMA5U23C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23A7N

  • MM# 970635
  • Spec Code SR8VG
  • Ordering Code 5CSEBA5U23A7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19C8N

  • MM# 973776
  • Spec Code SRBN5
  • Ordering Code 5CSEBA5U19C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23C6N

  • MM# 973778
  • Spec Code SRBN7
  • Ordering Code 5CSEBA5U23C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U23I7LN

  • MM# 984770
  • Spec Code SRESG
  • Ordering Code 5CSEBA5U23I7LN
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CSEA5 FPGA 5CSEBA5U19I7LN

  • MM# 999LG8
  • Spec Code SRGN9
  • Ordering Code 5CSEBA5U19I7LN
  • Stepping A1
  • ECCN EAR99

Trade compliance information

  • ECCN Varies By Product
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SRGN9

SR7J7

SR7J5

SR7NC

SRBN7

SR7NA

SR8VG

SRBN5

SR6WW

SR6WV

SR70N

SR4SR

SR4SQ

SR54Q

SR6X2

SR70U

SR7N3

SR70T

SR7MQ

SR7N2

SR7N1

SRESG

SR70Q

SR70P

SR6X0

SR4SL

SR50H

SR50G

SR50F

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.