Cyclone® V 5CSEA2 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19C8N

  • MM# 965715
  • Spec Code SR4SG
  • Ordering Code 5CSEBA2U19C8N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19C8SN

  • MM# 965716
  • Spec Code SR4SH
  • Ordering Code 5CSEBA2U19C8SN
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEMA2U23I7N

  • MM# 965722
  • Spec Code SR4SP
  • Ordering Code 5CSEMA2U23I7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19A7N

  • MM# 965984
  • Spec Code SR50A
  • Ordering Code 5CSEBA2U19A7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23C7SN

  • MM# 965985
  • Spec Code SR50B
  • Ordering Code 5CSEBA2U23C7SN
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23I7

  • MM# 965986
  • Spec Code SR50C
  • Ordering Code 5CSEBA2U23I7
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEMA2U23C8N

  • MM# 966131
  • Spec Code SR54M
  • Ordering Code 5CSEMA2U23C8N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19I7SN

  • MM# 968364
  • Spec Code SR70F
  • Ordering Code 5CSEBA2U19I7SN
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23C6N

  • MM# 968365
  • Spec Code SR70G
  • Ordering Code 5CSEBA2U23C6N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23C8SN

  • MM# 968367
  • Spec Code SR70J
  • Ordering Code 5CSEBA2U23C8SN
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19C6N

  • MM# 968972
  • Spec Code SR7J0
  • Ordering Code 5CSEBA2U19C6N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23C8N

  • MM# 968973
  • Spec Code SR7J1
  • Ordering Code 5CSEBA2U23C8N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23I7N

  • MM# 968974
  • Spec Code SR7J2
  • Ordering Code 5CSEBA2U23I7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEMA2U23C7N

  • MM# 968992
  • Spec Code SR7JM
  • Ordering Code 5CSEMA2U23C7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEMA2U23A7N

  • MM# 969118
  • Spec Code SR7N9
  • Ordering Code 5CSEMA2U23A7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19I7N

  • MM# 970627
  • Spec Code SR8V8
  • Ordering Code 5CSEBA2U19I7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23A7N

  • MM# 970628
  • Spec Code SR8V9
  • Ordering Code 5CSEBA2U23A7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23C7N

  • MM# 970629
  • Spec Code SR8VA
  • Ordering Code 5CSEBA2U23C7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U23I7SN

  • MM# 970630
  • Spec Code SR8VB
  • Ordering Code 5CSEBA2U23I7SN
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19C7N

  • MM# 973768
  • Spec Code SRBN0
  • Ordering Code 5CSEBA2U19C7N
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEBA2U19C7SN

  • MM# 973769
  • Spec Code SRBN1
  • Ordering Code 5CSEBA2U19C7SN
  • Stepping A1

Cyclone® V 5CSEA2 FPGA 5CSEMA2U23C6N

  • MM# 973783
  • Spec Code SRBNC
  • Ordering Code 5CSEMA2U23C6N
  • Stepping A1

Trade compliance information

  • ECCN EAR99
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR4SP

SR70J

SR7J1

SR7J0

SR8V9

SR7JM

SR8V8

SRBNC

SR50A

SRBN1

SR8VB

SRBN0

SR8VA

SR7N9

SR7J2

SR54M

SR70G

SR70F

SR4SH

SR4SG

SR50C

SR50B

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.