Cyclone® V 5CGXC5 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CGXC5 FPGA 5CGXBC5C6F23C7N

  • MM# 965696
  • Spec Code SR4RX
  • Ordering Code 5CGXBC5C6F23C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6M13I7N

  • MM# 965707
  • Spec Code SR4S8
  • Ordering Code 5CGXFC5C6M13I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXFC5F6M11I7N

  • MM# 965708
  • Spec Code SR4S9
  • Ordering Code 5CGXFC5F6M11I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXBC5C6U19C7N

  • MM# 965961
  • Spec Code SR4ZN
  • Ordering Code 5CGXBC5C6U19C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXBC5C7F27C8N

  • MM# 965962
  • Spec Code SR4ZP
  • Ordering Code 5CGXBC5C7F27C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXBC5C7U19C8N

  • MM# 968215
  • Spec Code SR6W4
  • Ordering Code 5CGXBC5C7U19C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6F23C7N

  • MM# 968222
  • Spec Code SR6WB
  • Ordering Code 5CGXFC5C6F23C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6U19A7N

  • MM# 968223
  • Spec Code SR6WC
  • Ordering Code 5CGXFC5C6U19A7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6U19C6N

  • MM# 968224
  • Spec Code SR6WD
  • Ordering Code 5CGXFC5C6U19C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5F7M11C8N

  • MM# 968225
  • Spec Code SR6WE
  • Ordering Code 5CGXFC5F7M11C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXBC5C7F23C8N

  • MM# 968354
  • Spec Code SR705
  • Ordering Code 5CGXBC5C7F23C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6F23I7N

  • MM# 968776
  • Spec Code SR7CC
  • Ordering Code 5CGXFC5C6F23I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6F23C6N

  • MM# 968918
  • Spec Code SR7GF
  • Ordering Code 5CGXFC5C6F23C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6U19I7N

  • MM# 968920
  • Spec Code SR7GH
  • Ordering Code 5CGXFC5C6U19I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6M13C7N

  • MM# 968921
  • Spec Code SR7GG
  • Ordering Code 5CGXFC5C6M13C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXFC5C7F27C8N

  • MM# 968923
  • Spec Code SR7GJ
  • Ordering Code 5CGXFC5C7F27C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6F27C6N

  • MM# 968987
  • Spec Code SR7JC
  • Ordering Code 5CGXFC5C6F27C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C7U19C8N

  • MM# 969100
  • Spec Code SR7MT
  • Ordering Code 5CGXFC5C7U19C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXBC5C6F27C7N

  • MM# 970605
  • Spec Code SR8UL
  • Ordering Code 5CGXBC5C6F27C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6F23A7N

  • MM# 970613
  • Spec Code SR8UU
  • Ordering Code 5CGXFC5C6F23A7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6F27I7N

  • MM# 970614
  • Spec Code SR8UV
  • Ordering Code 5CGXFC5C6F27I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6M13C6N

  • MM# 970615
  • Spec Code SR8UW
  • Ordering Code 5CGXFC5C6M13C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXFC5C7M13C8N

  • MM# 970616
  • Spec Code SR8UX
  • Ordering Code 5CGXFC5C7M13C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXFC5F6M11C6N

  • MM# 970617
  • Spec Code SR8UY
  • Ordering Code 5CGXFC5F6M11C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXFC5F6M11C7N

  • MM# 970618
  • Spec Code SR8UZ
  • Ordering Code 5CGXFC5F6M11C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6F27C7N

  • MM# 973760
  • Spec Code SRBMT
  • Ordering Code 5CGXFC5C6F27C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C6U19C7N

  • MM# 973762
  • Spec Code SRBMU
  • Ordering Code 5CGXFC5C6U19C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC5 FPGA 5CGXFC5C7F23C8N

  • MM# 973763
  • Spec Code SRBMV
  • Ordering Code 5CGXFC5C7F23C8N
  • Stepping A1
  • ECCN 3A991

Trade compliance information

  • ECCN Varies By Product
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR6W4

SR7JC

SR705

SR4RX

SR4S9

SR4S8

SRBMV

SR4ZP

SRBMU

SRBMT

SR4ZN

SR7GF

SR8UL

SR7MT

SR8UZ

SR8UY

SR8UX

SR7GJ

SR8UW

SR8UV

SR7GH

SR8UU

SR7CC

SR7GG

SR6WE

SR6WD

SR6WC

SR6WB

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.