Cyclone® V 5CGXC4 FPGA

0 Retailers X

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F23C6N

  • MM# 973756
  • Spec Code SRBMP
  • Ordering Code 5CGXFC4C6F23C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4F6M11C6N

  • MM# 968774
  • Spec Code SR7CA
  • Ordering Code 5CGXFC4F6M11C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6U19A7N

  • MM# 965971
  • Spec Code SR4ZY
  • Ordering Code 5CGXFC4C6U19A7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXBC4C6F27C7N

  • MM# 968491
  • Spec Code SR73Z
  • Ordering Code 5CGXBC4C6F27C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXBC4C7U19C8N

  • MM# 968214
  • Spec Code SR6W3
  • Ordering Code 5CGXBC4C7U19C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXBC4C6F23C7N

  • MM# 968353
  • Spec Code SR704
  • Ordering Code 5CGXBC4C6F23C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6U19C7N

  • MM# 968219
  • Spec Code SR6W8
  • Ordering Code 5CGXFC4C6U19C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4F7M11C8N

  • MM# 968359
  • Spec Code SR70A
  • Ordering Code 5CGXFC4F7M11C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6U19I7N

  • MM# 968916
  • Spec Code SR7GD
  • Ordering Code 5CGXFC4C6U19I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4F6M11I7

  • MM# 970612
  • Spec Code SR8UT
  • Ordering Code 5CGXFC4F6M11I7
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4F6M11C7N

  • MM# 970611
  • Spec Code SR8US
  • Ordering Code 5CGXFC4F6M11C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F27I7

  • MM# 965706
  • Spec Code SR4S7
  • Ordering Code 5CGXFC4C6F27I7
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C7F23C8N

  • MM# 968772
  • Spec Code SR7C8
  • Ordering Code 5CGXFC4C7F23C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6M13I7N

  • MM# 973758
  • Spec Code SRBMR
  • Ordering Code 5CGXFC4C6M13I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F23C7N

  • MM# 968771
  • Spec Code SR7C7
  • Ordering Code 5CGXFC4C6F23C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6M13C6N

  • MM# 965970
  • Spec Code SR4ZX
  • Ordering Code 5CGXFC4C6M13C6N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXBC4C7F23C8N

  • MM# 968908
  • Spec Code SR7G5
  • Ordering Code 5CGXBC4C7F23C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXBC4C6U19C7N

  • MM# 965694
  • Spec Code SR4RV
  • Ordering Code 5CGXBC4C6U19C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXBC4C7F27C8N

  • MM# 965695
  • Spec Code SR4RW
  • Ordering Code 5CGXBC4C7F27C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F23I7

  • MM# 999J5Z
  • Spec Code SRGCK
  • Ordering Code 5CGXFC4C6F23I7
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4F6M11I7N

  • MM# 968221
  • Spec Code SR6WA
  • Ordering Code 5CGXFC4F6M11I7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6U19C6N

  • MM# 965972
  • Spec Code SR4ZZ
  • Ordering Code 5CGXFC4C6U19C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F27C6N

  • MM# 968218
  • Spec Code SR6W7
  • Ordering Code 5CGXFC4C6F27C6N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F23I7N

  • MM# 965705
  • Spec Code SR4S6
  • Ordering Code 5CGXFC4C6F23I7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C7M13C8N

  • MM# 970610
  • Spec Code SR8UR
  • Ordering Code 5CGXFC4C7M13C8N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4C7F27C8N

  • MM# 968220
  • Spec Code SR6W9
  • Ordering Code 5CGXFC4C7F27C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C7U19C8N

  • MM# 968919
  • Spec Code SR7GE
  • Ordering Code 5CGXFC4C7U19C8N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6M13C7N

  • MM# 968917
  • Spec Code SR7GC
  • Ordering Code 5CGXFC4C6M13C7N
  • Stepping A1
  • ECCN EAR99

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F27C7N

  • MM# 968915
  • Spec Code SR7GB
  • Ordering Code 5CGXFC4C6F27C7N
  • Stepping A1
  • ECCN 3A991

Cyclone® V 5CGXC4 FPGA 5CGXFC4C6F27I7N

  • MM# 973757
  • Spec Code SRBMQ
  • Ordering Code 5CGXFC4C6F27I7N
  • Stepping A1
  • ECCN 3A991

Trade compliance information

  • ECCN Varies By Product
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR6W7

SR4ZZ

SR4ZY

SR6W3

SR4ZX

SRGCK

SR73Z

SR704

SR4RW

SR4S7

SR4RV

SR6W9

SR6W8

SR4S6

SRBMQ

SRBMP

SRBMR

SR8US

SR7CA

SR8UR

SR7GE

SR7GD

SR7GC

SR7GB

SR8UT

SR7G5

SR6WA

SR7C8

SR7C7

SR70A

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.