Cyclone® V 5CGTD9 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Cyclone® V 5CGTD9 FPGA 5CGTFD9A5U19C7N

  • MM# 965690
  • Spec Code SR4RR
  • Ordering Code 5CGTFD9A5U19C7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9D5F27I7

  • MM# 965691
  • Spec Code SR4RS
  • Ordering Code 5CGTFD9D5F27I7
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9E5F35C7N

  • MM# 965959
  • Spec Code SR4ZL
  • Ordering Code 5CGTFD9E5F35C7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9A5U19I7N

  • MM# 968075
  • Spec Code SR6S1
  • Ordering Code 5CGTFD9A5U19I7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9C5F23C7N

  • MM# 968076
  • Spec Code SR6S2
  • Ordering Code 5CGTFD9C5F23C7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9E5F31I7N

  • MM# 968077
  • Spec Code SR6S3
  • Ordering Code 5CGTFD9E5F31I7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9E5F31C7N

  • MM# 968213
  • Spec Code SR6W2
  • Ordering Code 5CGTFD9E5F31C7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9D5F27C7N

  • MM# 968350
  • Spec Code SR701
  • Ordering Code 5CGTFD9D5F27C7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9E5F35I7N

  • MM# 968906
  • Spec Code SR7G3
  • Ordering Code 5CGTFD9E5F35I7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9A5U19A7N

  • MM# 970603
  • Spec Code SR8UJ
  • Ordering Code 5CGTFD9A5U19A7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9D5F27I7N

  • MM# 970604
  • Spec Code SR8UK
  • Ordering Code 5CGTFD9D5F27I7N
  • Stepping A1

Cyclone® V 5CGTD9 FPGA 5CGTFD9C5F23I7N

  • MM# 973754
  • Spec Code SRBMM
  • Ordering Code 5CGTFD9C5F23I7N
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR4ZL

SR6S3

SR4RS

SR6S2

SR4RR

SR6S1

SR7G3

SRBMM

SR6W2

SR8UK

SR8UJ

SR701

Drivers and Software

Latest Drivers & Software

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Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.