Intel® Cyclone® 10 10CL040 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel® Cyclone® 10 10CL040 FPGA 10CL040YF484I7G

  • MM# 965238
  • Spec Code SR4CV
  • Ordering Code 10CL040YF484I7G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040YU484I7G

  • MM# 965239
  • Spec Code SR4CW
  • Ordering Code 10CL040YU484I7G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040ZF484I8G

  • MM# 965240
  • Spec Code SR4CX
  • Ordering Code 10CL040ZF484I8G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040YF484C6G

  • MM# 965472
  • Spec Code SR4KH
  • Ordering Code 10CL040YF484C6G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040ZU484I8G

  • MM# 967115
  • Spec Code SR5YP
  • Ordering Code 10CL040ZU484I8G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040YU484C8G

  • MM# 967738
  • Spec Code SR6GM
  • Ordering Code 10CL040YU484C8G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040YU484C6G

  • MM# 968801
  • Spec Code SR7D1
  • Ordering Code 10CL040YU484C6G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040YF484C8G

  • MM# 973651
  • Spec Code SRBJN
  • Ordering Code 10CL040YF484C8G
  • Stepping A1

Intel® Cyclone® 10 10CL040 FPGA 10CL040YU484A7G

  • MM# 999A2G
  • Spec Code SRF4W
  • Ordering Code 10CL040YU484A7G
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SRBJN

SR7D1

SR4KH

SR5YP

SR6GM

SR4CX

SRF4W

SR4CW

SR4CV

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.