Intel® Cyclone® 10 10CL010 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel® Cyclone® 10 10CL010 FPGA 10CL010YE144C6G

  • MM# 965226
  • Spec Code SR4CH
  • Ordering Code 10CL010YE144C6G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YM164C6G

  • MM# 965227
  • Spec Code SR4CJ
  • Ordering Code 10CL010YM164C6G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YU256C6G

  • MM# 965228
  • Spec Code SR4CK
  • Ordering Code 10CL010YU256C6G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010ZU256I8G

  • MM# 965229
  • Spec Code SR4CL
  • Ordering Code 10CL010ZU256I8G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010ZE144I8G

  • MM# 965563
  • Spec Code SR4N4
  • Ordering Code 10CL010ZE144I8G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YM164C8G

  • MM# 967111
  • Spec Code SR5YK
  • Ordering Code 10CL010YM164C8G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YE144C8G

  • MM# 967735
  • Spec Code SR6GJ
  • Ordering Code 10CL010YE144C8G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YU256I7G

  • MM# 967736
  • Spec Code SR6GK
  • Ordering Code 10CL010YU256I7G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YM164I7G

  • MM# 968086
  • Spec Code SR6SC
  • Ordering Code 10CL010YM164I7G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YU256C8G

  • MM# 968087
  • Spec Code SR6SD
  • Ordering Code 10CL010YU256C8G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010ZM164I8G

  • MM# 968795
  • Spec Code SR7CV
  • Ordering Code 10CL010ZM164I8G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YE144I7G

  • MM# 973648
  • Spec Code SRBJK
  • Ordering Code 10CL010YE144I7G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YM164A7G

  • MM# 999A24
  • Spec Code SRF4P
  • Ordering Code 10CL010YM164A7G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YU256A7G

  • MM# 999A25
  • Spec Code SRF4Q
  • Ordering Code 10CL010YU256A7G
  • Stepping A1

Intel® Cyclone® 10 10CL010 FPGA 10CL010YE144A7G

  • MM# 999A2N
  • Spec Code SRF52
  • Ordering Code 10CL010YE144A7G
  • Stepping A1

Trade compliance information

  • ECCN EAR99
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR4CL

SR4CK

SR4CJ

SR4N4

SR6GK

SR4CH

SR6GJ

SR6SC

SRBJK

SRF4Q

SRF52

SRF4P

SR7CV

SR5YK

SR6SD

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.