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  • Brand Name: Core Ultra

  • Product Number: 6526Y

  • Ordering Code: PK8072205559500

  • SPEC Code: SRN6N

  • Code Name: Emerald Rapids

Arria® V 5ASXB5 FPGA

Specifications

Export specifications

Essentials

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Arria® V 5ASXB5 FPGA 5ASXBB5D4F31C4G

  • MM# 999XDW
  • Spec Code SRHCC
  • Ordering Code 5ASXBB5D4F31C4G
  • Stepping A1
  • MDDS Content IDs 725258

Arria® V 5ASXB5 FPGA 5ASXBB5D4F31C5G

  • MM# 999XDX
  • Spec Code SRHCD
  • Ordering Code 5ASXBB5D4F31C5G
  • Stepping A1
  • MDDS Content IDs 725177

Arria® V 5ASXB5 FPGA 5ASXBB5D4F31I5G

  • MM# 999XDZ
  • Spec Code SRHCE
  • Ordering Code 5ASXBB5D4F31I5G
  • Stepping A1
  • MDDS Content IDs 725543

Arria® V 5ASXB5 FPGA 5ASXBB5D4F35C4G

  • MM# 999XF1
  • Spec Code SRHCF
  • Ordering Code 5ASXBB5D4F35C4G
  • Stepping A1
  • MDDS Content IDs 725475

Arria® V 5ASXB5 FPGA 5ASXBB5D4F35C5G

  • MM# 999XF2
  • Spec Code SRHCG
  • Ordering Code 5ASXBB5D4F35C5G
  • Stepping A1
  • MDDS Content IDs 725577

Arria® V 5ASXB5 FPGA 5ASXBB5D4F35I5G

  • MM# 999XF3
  • Spec Code SRHCH
  • Ordering Code 5ASXBB5D4F35I5G
  • Stepping A1
  • MDDS Content IDs 724784

Arria® V 5ASXB5 FPGA 5ASXBB5D4F40C5G

  • MM# 999XF5
  • Spec Code SRHCK
  • Ordering Code 5ASXBB5D4F40C5G
  • Stepping A1
  • MDDS Content IDs 725149

Arria® V 5ASXB5 FPGA 5ASXBB5D4F40I5G

  • MM# 999XF6
  • Spec Code SRHCL
  • Ordering Code 5ASXBB5D4F40I5G
  • Stepping A1
  • MDDS Content IDs 725344

Arria® V 5ASXB5 FPGA 5ASXBB5D6F31C6G

  • MM# 999XF7
  • Spec Code SRHCM
  • Ordering Code 5ASXBB5D6F31C6G
  • Stepping A1
  • MDDS Content IDs 726161

Arria® V 5ASXB5 FPGA 5ASXBB5D6F35C6G

  • MM# 999XF8
  • Spec Code SRHCN
  • Ordering Code 5ASXBB5D6F35C6G
  • Stepping A1
  • MDDS Content IDs 725365

Arria® V 5ASXB5 FPGA 5ASXBB5D6F40C6G

  • MM# 999XF9
  • Spec Code SRHCP
  • Ordering Code 5ASXBB5D6F40C6G
  • Stepping A1
  • MDDS Content IDs 724974

Arria® V 5ASXB5 FPGA 5ASXFB5G4F35C4G

  • MM# 999XFP
  • Spec Code SRHD0
  • Ordering Code 5ASXFB5G4F35C4G
  • Stepping A1
  • MDDS Content IDs 725507

Arria® V 5ASXB5 FPGA 5ASXFB5G4F35C5G

  • MM# 999XFR
  • Spec Code SRHD1
  • Ordering Code 5ASXFB5G4F35C5G
  • Stepping A1
  • MDDS Content IDs 725079

Arria® V 5ASXB5 FPGA 5ASXFB5G4F35I3G

  • MM# 999XFT
  • Spec Code SRHD2
  • Ordering Code 5ASXFB5G4F35I3G
  • Stepping A1
  • MDDS Content IDs 691802

Arria® V 5ASXB5 FPGA 5ASXFB5G4F35I5G

  • MM# 999XFW
  • Spec Code SRHD3
  • Ordering Code 5ASXFB5G4F35I5G
  • Stepping A1
  • MDDS Content IDs 725514

Arria® V 5ASXB5 FPGA 5ASXFB5G6F35C6G

  • MM# 999XFX
  • Spec Code SRHD4
  • Ordering Code 5ASXFB5G6F35C6G
  • Stepping A1
  • MDDS Content IDs 725476

Arria® V 5ASXB5 FPGA 5ASXFB5H4F40C4G

  • MM# 999XFZ
  • Spec Code SRHD5
  • Ordering Code 5ASXFB5H4F40C4G
  • Stepping A1
  • MDDS Content IDs 725089

Arria® V 5ASXB5 FPGA 5ASXFB5H4F40C5G

  • MM# 999XG0
  • Spec Code SRHD6
  • Ordering Code 5ASXFB5H4F40C5G
  • Stepping A1
  • MDDS Content IDs 726170

Arria® V 5ASXB5 FPGA 5ASXFB5H4F40I3G

  • MM# 999XG1
  • Spec Code SRHD7
  • Ordering Code 5ASXFB5H4F40I3G
  • Stepping A1
  • MDDS Content IDs 693347

Arria® V 5ASXB5 FPGA 5ASXFB5H4F40I5G

  • MM# 999XG2
  • Spec Code SRHD8
  • Ordering Code 5ASXFB5H4F40I5G
  • Stepping A1
  • MDDS Content IDs 725975

Arria® V 5ASXB5 FPGA 5ASXFB5H6F40C6G

  • MM# 999XG3
  • Spec Code SRHD9
  • Ordering Code 5ASXFB5H6F40C6G
  • Stepping A1
  • MDDS Content IDs 725289

Arria® V 5ASXB5 FPGA 5ASXMB5E4F31C4G

  • MM# 999XGG
  • Spec Code SRHDK
  • Ordering Code 5ASXMB5E4F31C4G
  • Stepping A1
  • MDDS Content IDs 725039

Arria® V 5ASXB5 FPGA 5ASXMB5E4F31C5G

  • MM# 999XGH
  • Spec Code SRHDL
  • Ordering Code 5ASXMB5E4F31C5G
  • Stepping A1
  • MDDS Content IDs 725175

Arria® V 5ASXB5 FPGA 5ASXMB5E4F31I3G

  • MM# 999XGJ
  • Spec Code SRHDM
  • Ordering Code 5ASXMB5E4F31I3G
  • Stepping A1
  • MDDS Content IDs 726214

Arria® V 5ASXB5 FPGA 5ASXMB5E4F31I5G

  • MM# 999XGL
  • Spec Code SRHDN
  • Ordering Code 5ASXMB5E4F31I5G
  • Stepping A1
  • MDDS Content IDs 725424

Arria® V 5ASXB5 FPGA 5ASXMB5E6F31C6G

  • MM# 999XGM
  • Spec Code SRHDP
  • Ordering Code 5ASXMB5E6F31C6G
  • Stepping A1
  • MDDS Content IDs 726121

Arria® V 5ASXB5 FPGA 5ASXMB5G4F40C4G

  • MM# 999XGN
  • Spec Code SRHDQ
  • Ordering Code 5ASXMB5G4F40C4G
  • Stepping A1
  • MDDS Content IDs 725399,  746118

Arria® V 5ASXB5 FPGA 5ASXMB5G4F40C5G

  • MM# 999XGP
  • Spec Code SRHDR
  • Ordering Code 5ASXMB5G4F40C5G
  • Stepping A1
  • MDDS Content IDs 726114

Arria® V 5ASXB5 FPGA 5ASXMB5G4F40I5G

  • MM# 999XGR
  • Spec Code SRHDS
  • Ordering Code 5ASXMB5G4F40I5G
  • Stepping A1
  • MDDS Content IDs 726169

Arria® V 5ASXB5 FPGA 5ASXMB5G6F40C6G

  • MM# 999XGT
  • Spec Code SRHDT
  • Ordering Code 5ASXMB5G6F40C6G
  • Stepping A1
  • MDDS Content IDs 725920

Arria® V 5ASXB5 FPGA 5ASXBB5D4F40C4G

  • MM# 999ZZJ
  • Spec Code SRJ7W
  • Ordering Code 5ASXBB5D4F40C4G
  • Stepping A1
  • MDDS Content IDs 724885

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN Information

SRHD2

SRHD0

SRHCN

SRHCH

SRHCG

SRHD3

Drivers and Software

Latest Drivers & Software

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Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count†

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers†

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate†

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.

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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.

Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.

Refer to Datasheet for formal definitions of product properties and features.

‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.

“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.