Arria® V 5ASXB3 FPGA

0 Retailers X

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Arria® V 5ASXB3 FPGA 5ASXBB3D4F35I5G

  • MM# 999XDL
  • Spec Code SRHC5
  • Ordering Code 5ASXBB3D4F35I5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3G6F40C6G

  • MM# 999XGF
  • Spec Code SRHDJ
  • Ordering Code 5ASXMB3G6F40C6G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F31C5G

  • MM# 999XDF
  • Spec Code SRHC1
  • Ordering Code 5ASXBB3D4F31C5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F31C4G

  • MM# 999XDD
  • Spec Code SRHC0
  • Ordering Code 5ASXBB3D4F31C4G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3G6F35C6G

  • MM# 999XFH
  • Spec Code SRHCU
  • Ordering Code 5ASXFB3G6F35C6G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D6F31C6G

  • MM# 999XDR
  • Spec Code SRHC9
  • Ordering Code 5ASXBB3D6F31C6G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3G4F35C4G

  • MM# 999XFA
  • Spec Code SRHCQ
  • Ordering Code 5ASXFB3G4F35C4G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3G4F40I5G

  • MM# 999XGD
  • Spec Code SRHDH
  • Ordering Code 5ASXMB3G4F40I5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F40C5G

  • MM# 999XDN
  • Spec Code SRHC7
  • Ordering Code 5ASXBB3D4F40C5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3E6F31C6G

  • MM# 999XG9
  • Spec Code SRHDE
  • Ordering Code 5ASXMB3E6F31C6G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F40C4G

  • MM# 999XDM
  • Spec Code SRHC6
  • Ordering Code 5ASXBB3D4F40C4G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3G4F35I5G

  • MM# 999XFG
  • Spec Code SRHCT
  • Ordering Code 5ASXFB3G4F35I5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F35C4G

  • MM# 999XDH
  • Spec Code SRHC3
  • Ordering Code 5ASXBB3D4F35C4G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3G4F40C4G

  • MM# 999XGA
  • Spec Code SRHDF
  • Ordering Code 5ASXMB3G4F40C4G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3H6F40C6G

  • MM# 999XFN
  • Spec Code SRHCZ
  • Ordering Code 5ASXFB3H6F40C6G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F31I5G

  • MM# 999XDG
  • Spec Code SRHC2
  • Ordering Code 5ASXBB3D4F31I5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3E4F31I3G

  • MM# 999XG6
  • Spec Code SRHDC
  • Ordering Code 5ASXMB3E4F31I3G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3H4F40C5G

  • MM# 999XFK
  • Spec Code SRHCW
  • Ordering Code 5ASXFB3H4F40C5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F35C5G

  • MM# 999XDJ
  • Spec Code SRHC4
  • Ordering Code 5ASXBB3D4F35C5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3E4F31C5G

  • MM# 999XG5
  • Spec Code SRHDB
  • Ordering Code 5ASXMB3E4F31C5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3G4F35C5G

  • MM# 999XFC
  • Spec Code SRHCR
  • Ordering Code 5ASXFB3G4F35C5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3H4F40I3G

  • MM# 999XFL
  • Spec Code SRHCX
  • Ordering Code 5ASXFB3H4F40I3G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3H4F40C4G

  • MM# 999XFJ
  • Spec Code SRHCV
  • Ordering Code 5ASXFB3H4F40C4G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D4F40I5G

  • MM# 999XDP
  • Spec Code SRHC8
  • Ordering Code 5ASXBB3D4F40I5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3H4F40I5G

  • MM# 999XFM
  • Spec Code SRHCY
  • Ordering Code 5ASXFB3H4F40I5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXFB3G4F35I3G

  • MM# 999XFD
  • Spec Code SRHCS
  • Ordering Code 5ASXFB3G4F35I3G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D6F40C6G

  • MM# 999XDV
  • Spec Code SRHCB
  • Ordering Code 5ASXBB3D6F40C6G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXBB3D6F35C6G

  • MM# 999XDT
  • Spec Code SRHCA
  • Ordering Code 5ASXBB3D6F35C6G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3E4F31C4G

  • MM# 999XG4
  • Spec Code SRHDA
  • Ordering Code 5ASXMB3E4F31C4G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3E4F31I5G

  • MM# 999XG8
  • Spec Code SRHDD
  • Ordering Code 5ASXMB3E4F31I5G
  • Stepping A1

Arria® V 5ASXB3 FPGA 5ASXMB3G4F40C5G

  • MM# 999XGC
  • Spec Code SRHDG
  • Ordering Code 5ASXMB3G4F40C5G
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SRHCQ

SRHCY

SRHCX

SRHCW

SRHCV

SRHCU

SRHCT

SRHCS

SRHCR

SRHCA

SRHCB

SRHC1

SRHC0

SRHC9

SRHC8

SRHC7

SRHC6

SRHC5

SRHC4

SRHC3

SRHC2

SRHDB

SRHDA

SRHCZ

SRHDJ

SRHDH

SRHDG

SRHDF

SRHDE

SRHDD

SRHDC

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.