Arria® V 5AGXB3 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Arria® V 5AGXB3 FPGA 5AGXMB3G4F35I5G

  • MM# 965650
  • Spec Code SR4QL
  • Ordering Code 5AGXMB3G4F35I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXFB3H4F35I3G

  • MM# 965908
  • Spec Code SR4Y4
  • Ordering Code 5AGXFB3H4F35I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXFB3H4F40C5G

  • MM# 965909
  • Spec Code SR4Y5
  • Ordering Code 5AGXFB3H4F40C5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXBB3D4F35I5G

  • MM# 968292
  • Spec Code SR6YB
  • Ordering Code 5AGXBB3D4F35I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXFB3H4F35C4G

  • MM# 968300
  • Spec Code SR6YK
  • Ordering Code 5AGXFB3H4F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G4F40C5G

  • MM# 968315
  • Spec Code SR6Z0
  • Ordering Code 5AGXMB3G4F40C5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXFB3H4F35I5G

  • MM# 970561
  • Spec Code SR8TA
  • Ordering Code 5AGXFB3H4F35I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G4F31I3G

  • MM# 999FZC
  • Spec Code SRFK2
  • Ordering Code 5AGXMB3G4F31I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G4F31I5G

  • MM# 999FZD
  • Spec Code SRFK3
  • Ordering Code 5AGXMB3G4F31I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G4F35C4G

  • MM# 999FZF
  • Spec Code SRFK4
  • Ordering Code 5AGXMB3G4F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G4F35C5G

  • MM# 999FZH
  • Spec Code SRFK5
  • Ordering Code 5AGXMB3G4F35C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G4F40C4G

  • MM# 999FZJ
  • Spec Code SRFK6
  • Ordering Code 5AGXMB3G4F40C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXMB3G4F40I5G

  • MM# 999FZK
  • Spec Code SRFK7
  • Ordering Code 5AGXMB3G4F40I5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXMB3G6F31C6G

  • MM# 999FZL
  • Spec Code SRFK8
  • Ordering Code 5AGXMB3G6F31C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G6F35C6G

  • MM# 999FZM
  • Spec Code SRFK9
  • Ordering Code 5AGXMB3G6F35C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G6F40C6G

  • MM# 999FZN
  • Spec Code SRFKA
  • Ordering Code 5AGXMB3G6F40C6G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXBB3D4F31C4G

  • MM# 999G21
  • Spec Code SRFLZ
  • Ordering Code 5AGXBB3D4F31C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D4F31C5G

  • MM# 999G22
  • Spec Code SRFM0
  • Ordering Code 5AGXBB3D4F31C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D4F31I5G

  • MM# 999G23
  • Spec Code SRFM1
  • Ordering Code 5AGXBB3D4F31I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D4F35C4G

  • MM# 999G24
  • Spec Code SRFM2
  • Ordering Code 5AGXBB3D4F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D4F35C5G

  • MM# 999G25
  • Spec Code SRFM3
  • Ordering Code 5AGXBB3D4F35C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D4F40C4G

  • MM# 999G26
  • Spec Code SRFM4
  • Ordering Code 5AGXBB3D4F40C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXBB3D4F40C5G

  • MM# 999G27
  • Spec Code SRFM5
  • Ordering Code 5AGXBB3D4F40C5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXBB3D6F31C6G

  • MM# 999G29
  • Spec Code SRFM6
  • Ordering Code 5AGXBB3D6F31C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D6F35C6G

  • MM# 999G2A
  • Spec Code SRFM7
  • Ordering Code 5AGXBB3D6F35C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D6F40C6G

  • MM# 999G2C
  • Spec Code SRFM8
  • Ordering Code 5AGXBB3D6F40C6G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXFB3H4F35C5G

  • MM# 999G2W
  • Spec Code SRFMM
  • Ordering Code 5AGXFB3H4F35C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXFB3H4F40C4G

  • MM# 999G2X
  • Spec Code SRFMN
  • Ordering Code 5AGXFB3H4F40C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXFB3H4F40I3G

  • MM# 999G2Z
  • Spec Code SRFMP
  • Ordering Code 5AGXFB3H4F40I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXFB3H4F40I5G

  • MM# 999G30
  • Spec Code SRFMQ
  • Ordering Code 5AGXFB3H4F40I5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXFB3H6F35C6G

  • MM# 999G31
  • Spec Code SRFMR
  • Ordering Code 5AGXFB3H6F35C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXFB3H6F40C6G

  • MM# 999G33
  • Spec Code SRFMS
  • Ordering Code 5AGXFB3H6F40C6G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Arria® V 5AGXB3 FPGA 5AGXMB3G4F31C4G

  • MM# 999G53
  • Spec Code SRFP8
  • Ordering Code 5AGXMB3G4F31C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXMB3G4F31C5G

  • MM# 999G54
  • Spec Code SRFP9
  • Ordering Code 5AGXMB3G4F31C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Arria® V 5AGXB3 FPGA 5AGXBB3D4F40I5G

  • MM# 999G55
  • Spec Code SRFPA
  • Ordering Code 5AGXBB3D4F40I5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN/MDDS Information

SR4Y5

SR4Y4

SRFP9

SRFPA

SRFMM

SR8TA

SRFP8

SRFMS

SRFMR

SRFMQ

SRFMP

SRFMN

SRFK9

SRFLZ

SRFK8

SRFK7

SRFK6

SRFM8

SRFK5

SRFM7

SR4QL

SRFK4

SRFM6

SRFKA

SR6YB

SRFK3

SRFM5

SRFK2

SRFM4

SR6Z0

SRFM3

SRFM2

SRFM1

SRFM0

SR6YK

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.