Arria® V 5AGXA7 FPGA

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Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Arria® V 5AGXA7 FPGA 5AGXMA7G4F35I5G

  • MM# 999G4J
  • Spec Code SRFNV
  • Ordering Code 5AGXMA7G4F35I5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D6F31C6G

  • MM# 999G1J
  • Spec Code SRFLM
  • Ordering Code 5AGXBA7D6F31C6G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F31C4G

  • MM# 999G18
  • Spec Code SRFLF
  • Ordering Code 5AGXBA7D4F31C4G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F35C5G

  • MM# 999G1D
  • Spec Code SRFLJ
  • Ordering Code 5AGXBA7D4F35C5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXFA7H4F35C4G

  • MM# 999G2H
  • Spec Code SRFMC
  • Ordering Code 5AGXFA7H4F35C4G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D6F35C6G

  • MM# 999G1K
  • Spec Code SRFLN
  • Ordering Code 5AGXBA7D6F35C6G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F27C4G

  • MM# 999G13
  • Spec Code SRFLC
  • Ordering Code 5AGXBA7D4F27C4G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F35C4G

  • MM# 999FG2
  • Spec Code SRFFQ
  • Ordering Code 5AGXBA7D4F35C4G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G4F31I5G

  • MM# 999FZV
  • Spec Code SRFKE
  • Ordering Code 5AGXMA7G4F31I5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXFA7H4F35I5G

  • MM# 965905
  • Spec Code SR4Y1
  • Ordering Code 5AGXFA7H4F35I5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXFA7H4F35I3G

  • MM# 970556
  • Spec Code SR8T5
  • Ordering Code 5AGXFA7H4F35I3G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G4F31C5G

  • MM# 999G4D
  • Spec Code SRFNR
  • Ordering Code 5AGXMA7G4F31C5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G4F31C4G

  • MM# 999G4C
  • Spec Code SRFNQ
  • Ordering Code 5AGXMA7G4F31C4G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F31C5G

  • MM# 999G1A
  • Spec Code SRFLG
  • Ordering Code 5AGXBA7D4F31C5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G6F31C6G

  • MM# 999G4L
  • Spec Code SRFNW
  • Ordering Code 5AGXMA7G6F31C6G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G4F35C5G

  • MM# 999G4H
  • Spec Code SRFNU
  • Ordering Code 5AGXMA7G4F35C5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7D4F27C5G

  • MM# 999G47
  • Spec Code SRFNL
  • Ordering Code 5AGXMA7D4F27C5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F35I5G

  • MM# 999G1F
  • Spec Code SRFLK
  • Ordering Code 5AGXBA7D4F35I5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D6F27C6G

  • MM# 999G1G
  • Spec Code SRFLL
  • Ordering Code 5AGXBA7D6F27C6G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXFA7H4F35C5G

  • MM# 978995
  • Spec Code SRCZC
  • Ordering Code 5AGXFA7H4F35C5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7D4F27I5G

  • MM# 999G49
  • Spec Code SRFNN
  • Ordering Code 5AGXMA7D4F27I5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F27I5G

  • MM# 999G17
  • Spec Code SRFLE
  • Ordering Code 5AGXBA7D4F27I5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F31I5G

  • MM# 999G1C
  • Spec Code SRFLH
  • Ordering Code 5AGXBA7D4F31I5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7D4F27I3G

  • MM# 999G48
  • Spec Code SRFNM
  • Ordering Code 5AGXMA7D4F27I3G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G4F31I3G

  • MM# 999G4F
  • Spec Code SRFNS
  • Ordering Code 5AGXMA7G4F31I3G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXBA7D4F27C5G

  • MM# 999G15
  • Spec Code SRFLD
  • Ordering Code 5AGXBA7D4F27C5G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXFA7H6F35C6G

  • MM# 999G2J
  • Spec Code SRFMD
  • Ordering Code 5AGXFA7H6F35C6G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7D6F27C6G

  • MM# 999G4A
  • Spec Code SRFNP
  • Ordering Code 5AGXMA7D6F27C6G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7D4F27C4G

  • MM# 999G45
  • Spec Code SRFNK
  • Ordering Code 5AGXMA7D4F27C4G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G6F35C6G

  • MM# 999G4M
  • Spec Code SRFNX
  • Ordering Code 5AGXMA7G6F35C6G
  • Stepping A1

Arria® V 5AGXA7 FPGA 5AGXMA7G4F35C4G

  • MM# 999G4G
  • Spec Code SRFNT
  • Ordering Code 5AGXMA7G4F35C4G
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SRFLD

SRFLC

SRFKE

SR4Y1

SRCZC

SRFFQ

SRFNX

SRFNW

SRFMD

SRFMC

SR8T5

SRFLL

SRFNN

SRFLK

SRFNM

SRFLJ

SRFNL

SRFNK

SRFLH

SRFLG

SRFLF

SRFLE

SRFNV

SRFNU

SRFNT

SRFNS

SRFNR

SRFNQ

SRFLN

SRFNP

SRFLM

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.