Intel® Arria® 10 SX 660 FPGA
Specifications
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Essentials
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Product Collection
Intel® Arria® 10 SX SoC FPGA
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Marketing Status
Launched
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Launch Date
2013
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Lithography
20 nm
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Resources
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Logic Elements (LE)
660000
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Adaptive Logic Modules (ALM)
250540
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Adaptive Logic Module (ALM) Registers
1002160
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Fabric and I/O Phase-Locked Loops (PLLs)
32
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Maximum Embedded Memory
47.7 Mb
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Digital Signal Processing (DSP) Blocks
1687
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Digital Signal Processing (DSP) Format
Multiply, Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Processor System (HPS)
Dual-core Arm* Cortex*-A9
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, QDR II, QDR II+, QDR IV, LPDDR3, DDR3L
I/O Specifications
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Maximum User I/O Count†
696
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
270
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Maximum Non-Return to Zero (NRZ) Transceivers†
48
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Maximum Non-Return to Zero (NRZ) Data Rate†
17.4 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Advanced Technologies
Package Specifications
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Package Options
F1152, F1517
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Retired and discontinued
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SR45W
- 964993 PCN
SR45V
- 964992 PCN
SR45U
- 964991 PCN
SR45T
- 964989 PCN
SRBFB
- 973529 PCN
SR4BH
- 965188 PCN
SR45X
- 964994 PCN
SR4F5
- 965319 PCN
SR5XF
- 967066 PCN
SR4F4
- 965318 PCN
SR4F3
- 965317 PCN
SR4F2
- 965315 PCN
SR4F1
- 965314 PCN
SR5XM
- 967072 PCN
SR48Z
- 965101 PCN
SR48Y
- 965100 PCN
SR48X
- 965099 PCN
SR48W
- 965098 PCN
SRKFX
- 99A8RC PCN
SR494
- 965107 PCN
SRKFY
- 99A8RD PCN
SR60U
- 967193 PCN
SR5KP
- 966666 PCN
SR493
- 965106 PCN
SR492
- 965105 PCN
SR491
- 965103 PCN
SR60F
- 967180 PCN
SR490
- 965102 PCN
SR48L
- 965088 PCN
SR6DD
- 967624 PCN
SR489
- 965077 PCN
SR488
- 965076 PCN
SR487
- 965075 PCN
SR48A
- 965078 PCN
SR4DK
- 965263 PCN
SR4GY
- 965382 PCN
SR4GW
- 965380 PCN
SR4GV
- 965379 PCN
SRCZ7
- 978990 PCN
SR4GZ
- 965383 PCN
SR46X
- 965031 PCN
SR46W
- 965030 PCN
SRCYK
- 978967 PCN
SR46V
- 965029 PCN
SR46U
- 965028 PCN
SR46T
- 965026 PCN
SR46R
- 965023 PCN
SR473
- 965037 PCN
SR46Q
- 965021 PCN
SRBFS
- 973546 PCN
SR4H1
- 965385 PCN
SR4H0
- 965384 PCN
SRBFJ
- 973537 PCN
SRBFH
- 973536 PCN
SR4G6
- 965356 PCN
SRBFE
- 973532 PCN
SRBFC
- 973530 PCN
SR46P
- 965020 PCN
SRBFR
- 973545 PCN
SRBFQ
- 973544 PCN
SRBFP
- 973543 PCN
SRBFN
- 973542 PCN
SR58L
- 966266 PCN
SRBFM
- 973541 PCN
SRBFL
- 973539 PCN
SRBFK
- 973538 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.