Intel® Arria® 10 GX 480 FPGA
Specifications
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Essentials
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Product Collection
Intel® Arria® 10 GX FPGA
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Marketing Status
Launched
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Launch Date
2013
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Lithography
20 nm
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Resources
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Logic Elements (LE)
480000
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Adaptive Logic Modules (ALM)
181790
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Adaptive Logic Module (ALM) Registers
727160
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Fabric and I/O Phase-Locked Loops (PLLs)
24
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Maximum Embedded Memory
32.3 Mb
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Digital Signal Processing (DSP) Blocks
1368
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Digital Signal Processing (DSP) Format
Multiply, Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, QDR II, QDR II+, RLDRAM 3, QDR IV, LPDDR3, DDR3L
I/O Specifications
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Maximum User I/O Count†
492
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
222
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Maximum Non-Return to Zero (NRZ) Transceivers†
36
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Maximum Non-Return to Zero (NRZ) Data Rate†
17.4 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Advanced Technologies
Package Specifications
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Package Options
F780, F1152
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Intel® Arria® 10 GX 480 FPGA 10AX048H4F34E3VG
- MM# 965411
- Spec Code SR4HT
- Ordering Code 10AX048H4F34E3VG
- Stepping A1
- ECCN 3A991
- CCATS NA
Intel® Arria® 10 GX 480 FPGA 10AX048H4F34I3VG
- MM# 973583
- Spec Code SRBGU
- Ordering Code 10AX048H4F34I3VG
- Stepping A1
- ECCN 3A991
- CCATS NA
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SR49Z
- 965136 PCN
SR49Y
- 965135 PCN
SR49X
- 965134 PCN
SR49W
- 965133 PCN
SR4B4
- 965175 PCN
SR6F6
- 967688 PCN
SR4B3
- 965174 PCN
SR6F5
- 967687 PCN
SR4B2
- 965173 PCN
SR6F4
- 967686 PCN
SR4B1
- 965172 PCN
SR6F3
- 967684 PCN
SR4B0
- 965171 PCN
SR6F2
- 967683 PCN
SR6F1
- 967682 PCN
SR6F8
- 967690 PCN
SR4B5
- 965176 PCN
SR6F7
- 967689 PCN
SR4A2
- 965139 PCN
SR4A1
- 965138 PCN
SR4HX
- 965415 PCN
SR4A0
- 965137 PCN
SR4HW
- 965414 PCN
SR4HV
- 965413 PCN
SR4HU
- 965412 PCN
SR4HT
- 965411 PCN
SR4HS
- 965410 PCN
SR6DZ
- 967645 PCN
SR6DY
- 967644 PCN
SR6DX
- 967643 PCN
SR6DW
- 967642 PCN
SR6DV
- 967641 PCN
SRBGV
- 973584 PCN
SRBGU
- 973583 PCN
SRBGT
- 973582 PCN
SR4L9
- 965498 PCN
SRBGS
- 973581 PCN
SR4LE
- 965504 PCN
SRBGR
- 973580 PCN
SR4LD
- 965503 PCN
SR4LC
- 965502 PCN
SR4LB
- 965501 PCN
SR4LA
- 965499 PCN
SR58Y
- 966278 PCN
SR58X
- 966277 PCN
SR58W
- 966276 PCN
SR58V
- 966275 PCN
SR58Z
- 966279 PCN
SR592
- 966282 PCN
SR591
- 966281 PCN
SR590
- 966280 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.