Stratix® V 5SGXB5 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40C2LG

  • MM# 999Z11
  • Spec Code SRHQ8
  • Ordering Code 5SGXEB5R1F40C2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40I2G

  • MM# 999Z12
  • Spec Code SRHQ9
  • Ordering Code 5SGXEB5R1F40I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F43C1G

  • MM# 999Z13
  • Spec Code SRHQA
  • Ordering Code 5SGXEB5R1F43C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F43C2G

  • MM# 999Z14
  • Spec Code SRHQB
  • Ordering Code 5SGXEB5R1F43C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F43I2G

  • MM# 999Z1P
  • Spec Code SRHQT
  • Ordering Code 5SGXEB5R1F43I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C2G

  • MM# 999Z24
  • Spec Code SRHR3
  • Ordering Code 5SGXEB5R2F40C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F43C3G

  • MM# 999Z26
  • Spec Code SRHR5
  • Ordering Code 5SGXEB5R2F43C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C2G

  • MM# 999Z27
  • Spec Code SRHR6
  • Ordering Code 5SGXEB5R3F40C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40I3G

  • MM# 999Z28
  • Spec Code SRHR7
  • Ordering Code 5SGXEB5R3F40I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F43C2G

  • MM# 999Z29
  • Spec Code SRHR8
  • Ordering Code 5SGXEB5R3F43C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40C1G

  • MM# 999Z2L
  • Spec Code SRHRG
  • Ordering Code 5SGXEB5R1F40C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F43C3G

  • MM# 999Z2N
  • Spec Code SRHRJ
  • Ordering Code 5SGXEB5R3F43C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C1G

  • MM# 999Z98
  • Spec Code SRHW1
  • Ordering Code 5SGXEB5R2F40C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C2LG

  • MM# 999Z99
  • Spec Code SRHW2
  • Ordering Code 5SGXEB5R2F40C2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I3G

  • MM# 999Z9C
  • Spec Code SRHW3
  • Ordering Code 5SGXEB5R2F40I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F43C1G

  • MM# 999Z9D
  • Spec Code SRHW4
  • Ordering Code 5SGXEB5R2F43C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F43C2G

  • MM# 999Z9F
  • Spec Code SRHW5
  • Ordering Code 5SGXEB5R2F43C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C2LG

  • MM# 999Z9J
  • Spec Code SRHW8
  • Ordering Code 5SGXEB5R3F40C2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C4G

  • MM# 999Z9K
  • Spec Code SRHW9
  • Ordering Code 5SGXEB5R3F40C4G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40I4G

  • MM# 999Z9L
  • Spec Code SRHWA
  • Ordering Code 5SGXEB5R3F40I4G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F43I3G

  • MM# 999Z9M
  • Spec Code SRHWB
  • Ordering Code 5SGXEB5R3F43I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F43I4G

  • MM# 999Z9N
  • Spec Code SRHWC
  • Ordering Code 5SGXEB5R3F43I4G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C1G

  • MM# 999ZCL
  • Spec Code SRHXS
  • Ordering Code 5SGXMB5R2F40C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C2G

  • MM# 999ZCM
  • Spec Code SRHXT
  • Ordering Code 5SGXMB5R2F40C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I2LG

  • MM# 999ZCP
  • Spec Code SRHXU
  • Ordering Code 5SGXMB5R2F40I2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I3G

  • MM# 999ZCR
  • Spec Code SRHXV
  • Ordering Code 5SGXMB5R2F40I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I3LG

  • MM# 999ZCT
  • Spec Code SRHXW
  • Ordering Code 5SGXMB5R2F40I3LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F43C1G

  • MM# 999ZCW
  • Spec Code SRHXX
  • Ordering Code 5SGXMB5R2F43C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F43C2G

  • MM# 999ZCX
  • Spec Code SRHXY
  • Ordering Code 5SGXMB5R2F43C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F43I2G

  • MM# 999ZDZ
  • Spec Code SRHYQ
  • Ordering Code 5SGXMB5R2F43I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F43I3G

  • MM# 999ZF0
  • Spec Code SRHYR
  • Ordering Code 5SGXMB5R2F43I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40I4G

  • MM# 999ZF1
  • Spec Code SRHYS
  • Ordering Code 5SGXMB5R3F40I4G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F43C3G

  • MM# 999ZF2
  • Spec Code SRHYT
  • Ordering Code 5SGXMB5R3F43C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F43I4G

  • MM# 999ZF3
  • Spec Code SRHYU
  • Ordering Code 5SGXMB5R3F43I4G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40C2G

  • MM# 999ZG1
  • Spec Code SRHZJ
  • Ordering Code 5SGXEB5R1F40C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C3G

  • MM# 999ZGD
  • Spec Code SRHZU
  • Ordering Code 5SGXEB5R2F40C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I2G

  • MM# 999ZGG
  • Spec Code SRHZV
  • Ordering Code 5SGXEB5R2F40I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I2LG

  • MM# 999ZGH
  • Spec Code SRHZW
  • Ordering Code 5SGXEB5R2F40I2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I3LG

  • MM# 999ZGJ
  • Spec Code SRHZX
  • Ordering Code 5SGXEB5R2F40I3LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F43I2G

  • MM# 999ZGK
  • Spec Code SRHZY
  • Ordering Code 5SGXEB5R2F43I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F43I3G

  • MM# 999ZGL
  • Spec Code SRHZZ
  • Ordering Code 5SGXEB5R2F43I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C3G

  • MM# 999ZGM
  • Spec Code SRJ00
  • Ordering Code 5SGXEB5R3F40C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40I3LG

  • MM# 999ZGN
  • Spec Code SRJ01
  • Ordering Code 5SGXEB5R3F40I3LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F43C4G

  • MM# 999ZGP
  • Spec Code SRJ02
  • Ordering Code 5SGXEB5R3F43C4G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40C2LG

  • MM# 999ZK2
  • Spec Code SRJ1T
  • Ordering Code 5SGXMB5R1F40C2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F43C1G

  • MM# 999ZK3
  • Spec Code SRJ1U
  • Ordering Code 5SGXMB5R1F43C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F43C2G

  • MM# 999ZK4
  • Spec Code SRJ1V
  • Ordering Code 5SGXMB5R1F43C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C3G

  • MM# 999ZK5
  • Spec Code SRJ1W
  • Ordering Code 5SGXMB5R2F40C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C2LG

  • MM# 999ZK6
  • Spec Code SRJ1X
  • Ordering Code 5SGXMB5R3F40C2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C3G

  • MM# 999ZK7
  • Spec Code SRJ1Y
  • Ordering Code 5SGXMB5R3F40C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40I3G

  • MM# 999ZK8
  • Spec Code SRJ1Z
  • Ordering Code 5SGXMB5R3F40I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F43I3G

  • MM# 999ZK9
  • Spec Code SRJ20
  • Ordering Code 5SGXMB5R3F43I3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40C1G

  • MM# 999ZMA
  • Spec Code SRJ3J
  • Ordering Code 5SGXMB5R1F40C1G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C2LG

  • MM# 999ZMD
  • Spec Code SRJ3L
  • Ordering Code 5SGXMB5R2F40C2LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F43C3G

  • MM# 999ZMG
  • Spec Code SRJ3N
  • Ordering Code 5SGXMB5R2F43C3G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C2G

  • MM# 999ZMH
  • Spec Code SRJ3P
  • Ordering Code 5SGXMB5R3F40C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C4G

  • MM# 999ZMJ
  • Spec Code SRJ3Q
  • Ordering Code 5SGXMB5R3F40C4G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40I3LG

  • MM# 999ZMK
  • Spec Code SRJ3R
  • Ordering Code 5SGXMB5R3F40I3LG
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F43C2G

  • MM# 999ZML
  • Spec Code SRJ3S
  • Ordering Code 5SGXMB5R3F43C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40C2G

  • MM# 999ZTA
  • Spec Code SRJ6J
  • Ordering Code 5SGXMB5R1F40C2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40I2G

  • MM# 999ZTC
  • Spec Code SRJ6K
  • Ordering Code 5SGXMB5R1F40I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F43I2G

  • MM# 999ZTD
  • Spec Code SRJ6L
  • Ordering Code 5SGXMB5R1F43I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I2G

  • MM# 999ZTF
  • Spec Code SRJ6M
  • Ordering Code 5SGXMB5R2F40I2G
  • Stepping A1

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F43C4G

  • MM# 999ZTJ
  • Spec Code SRJ6Q
  • Ordering Code 5SGXMB5R3F43C4G
  • Stepping A1

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SRHRG

SRHZJ

SRHYU

SRHYT

SRHYS

SRHYR

SRHYQ

SRHR8

SRHR7

SRHR6

SRHQT

SRHR5

SRHR3

SRHQ9

SRHQ8

SRHQB

SRHQA

SRHXV

SRJ3P

SRHXU

SRJ3Q

SRHXT

SRJ3R

SRHXS

SRJ00

SRJ3S

SRJ01

SRJ02

SRJ3J

SRJ3L

SRHXY

SRHXX

SRJ3N

SRHXW

SRJ6K

SRJ6L

SRJ6M

SRJ6Q

SRHWC

SRHWB

SRHWA

SRJ6J

SRJ1V

SRJ1W

SRJ1X

SRJ1Y

SRJ1Z

SRHW5

SRHZX

SRHW4

SRHZW

SRJ20

SRHW3

SRHZV

SRHW2

SRHZU

SRHW1

SRHRJ

SRJ1T

SRJ1U

SRHW9

SRHW8

SRHZZ

SRHZY

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.