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  • Brand Name: Core i7

  • Product Number: i7-12700KF

  • Ordering Code: CM8071504553829

  • SPEC Code: SRL4P

  • Code Name: Alder Lake

Stratix® V 5SGXB5 FPGA

Specifications

Export specifications

Essentials

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40C2LG

  • MM# 999Z11
  • Spec Code SRHQ8
  • Ordering Code 5SGXEB5R1F40C2LG
  • Stepping A1
  • MDDS Content IDs 725621

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40I2G

  • MM# 999Z12
  • Spec Code SRHQ9
  • Ordering Code 5SGXEB5R1F40I2G
  • Stepping A1
  • MDDS Content IDs 726091

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C2G

  • MM# 999Z24
  • Spec Code SRHR3
  • Ordering Code 5SGXEB5R2F40C2G
  • Stepping A1
  • MDDS Content IDs 725170

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C2G

  • MM# 999Z27
  • Spec Code SRHR6
  • Ordering Code 5SGXEB5R3F40C2G
  • Stepping A1
  • MDDS Content IDs 725923

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40I3G

  • MM# 999Z28
  • Spec Code SRHR7
  • Ordering Code 5SGXEB5R3F40I3G
  • Stepping A1
  • MDDS Content IDs 724852

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40C1G

  • MM# 999Z2L
  • Spec Code SRHRG
  • Ordering Code 5SGXEB5R1F40C1G
  • Stepping A1
  • MDDS Content IDs 724812

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C1G

  • MM# 999Z98
  • Spec Code SRHW1
  • Ordering Code 5SGXEB5R2F40C1G
  • Stepping A1
  • MDDS Content IDs 725638

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C2LG

  • MM# 999Z99
  • Spec Code SRHW2
  • Ordering Code 5SGXEB5R2F40C2LG
  • Stepping A1
  • MDDS Content IDs 725881

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I3G

  • MM# 999Z9C
  • Spec Code SRHW3
  • Ordering Code 5SGXEB5R2F40I3G
  • Stepping A1
  • MDDS Content IDs 724963

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C2LG

  • MM# 999Z9J
  • Spec Code SRHW8
  • Ordering Code 5SGXEB5R3F40C2LG
  • Stepping A1
  • MDDS Content IDs 725210

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C4G

  • MM# 999Z9K
  • Spec Code SRHW9
  • Ordering Code 5SGXEB5R3F40C4G
  • Stepping A1
  • MDDS Content IDs 726049

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40I4G

  • MM# 999Z9L
  • Spec Code SRHWA
  • Ordering Code 5SGXEB5R3F40I4G
  • Stepping A1
  • MDDS Content IDs 726226

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C1G

  • MM# 999ZCL
  • Spec Code SRHXS
  • Ordering Code 5SGXMB5R2F40C1G
  • Stepping A1
  • MDDS Content IDs 726208

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C2G

  • MM# 999ZCM
  • Spec Code SRHXT
  • Ordering Code 5SGXMB5R2F40C2G
  • Stepping A1
  • MDDS Content IDs 724839

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I2LG

  • MM# 999ZCP
  • Spec Code SRHXU
  • Ordering Code 5SGXMB5R2F40I2LG
  • Stepping A1
  • MDDS Content IDs 725944

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I3G

  • MM# 999ZCR
  • Spec Code SRHXV
  • Ordering Code 5SGXMB5R2F40I3G
  • Stepping A1
  • MDDS Content IDs 725588

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I3LG

  • MM# 999ZCT
  • Spec Code SRHXW
  • Ordering Code 5SGXMB5R2F40I3LG
  • Stepping A1
  • MDDS Content IDs 725650

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40I4G

  • MM# 999ZF1
  • Spec Code SRHYS
  • Ordering Code 5SGXMB5R3F40I4G
  • Stepping A1
  • MDDS Content IDs 724838

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40C2G

  • MM# 999ZG1
  • Spec Code SRHZJ
  • Ordering Code 5SGXEB5R1F40C2G
  • Stepping A1
  • MDDS Content IDs 726041

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C3G

  • MM# 999ZGD
  • Spec Code SRHZU
  • Ordering Code 5SGXEB5R2F40C3G
  • Stepping A1
  • MDDS Content IDs 724868

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I2G

  • MM# 999ZGG
  • Spec Code SRHZV
  • Ordering Code 5SGXEB5R2F40I2G
  • Stepping A1
  • MDDS Content IDs 725453

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I2LG

  • MM# 999ZGH
  • Spec Code SRHZW
  • Ordering Code 5SGXEB5R2F40I2LG
  • Stepping A1
  • MDDS Content IDs 725109

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I3LG

  • MM# 999ZGJ
  • Spec Code SRHZX
  • Ordering Code 5SGXEB5R2F40I3LG
  • Stepping A1
  • MDDS Content IDs 724924

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C3G

  • MM# 999ZGM
  • Spec Code SRJ00
  • Ordering Code 5SGXEB5R3F40C3G
  • Stepping A1
  • MDDS Content IDs 725968

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40I3LG

  • MM# 999ZGN
  • Spec Code SRJ01
  • Ordering Code 5SGXEB5R3F40I3LG
  • Stepping A1
  • MDDS Content IDs 726004

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40C2LG

  • MM# 999ZK2
  • Spec Code SRJ1T
  • Ordering Code 5SGXMB5R1F40C2LG
  • Stepping A1
  • MDDS Content IDs 725280

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C3G

  • MM# 999ZK5
  • Spec Code SRJ1W
  • Ordering Code 5SGXMB5R2F40C3G
  • Stepping A1
  • MDDS Content IDs 725204

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C2LG

  • MM# 999ZK6
  • Spec Code SRJ1X
  • Ordering Code 5SGXMB5R3F40C2LG
  • Stepping A1
  • MDDS Content IDs 726224

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C3G

  • MM# 999ZK7
  • Spec Code SRJ1Y
  • Ordering Code 5SGXMB5R3F40C3G
  • Stepping A1
  • MDDS Content IDs 725806

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40I3G

  • MM# 999ZK8
  • Spec Code SRJ1Z
  • Ordering Code 5SGXMB5R3F40I3G
  • Stepping A1
  • MDDS Content IDs 725626

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40C1G

  • MM# 999ZMA
  • Spec Code SRJ3J
  • Ordering Code 5SGXMB5R1F40C1G
  • Stepping A1
  • MDDS Content IDs 726283

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40C2LG

  • MM# 999ZMD
  • Spec Code SRJ3L
  • Ordering Code 5SGXMB5R2F40C2LG
  • Stepping A1
  • MDDS Content IDs 724775

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C2G

  • MM# 999ZMH
  • Spec Code SRJ3P
  • Ordering Code 5SGXMB5R3F40C2G
  • Stepping A1
  • MDDS Content IDs 725589

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C4G

  • MM# 999ZMJ
  • Spec Code SRJ3Q
  • Ordering Code 5SGXMB5R3F40C4G
  • Stepping A1
  • MDDS Content IDs 725907

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40I3LG

  • MM# 999ZMK
  • Spec Code SRJ3R
  • Ordering Code 5SGXMB5R3F40I3LG
  • Stepping A1
  • MDDS Content IDs 726047

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40C2G

  • MM# 999ZTA
  • Spec Code SRJ6J
  • Ordering Code 5SGXMB5R1F40C2G
  • Stepping A1
  • MDDS Content IDs 725134

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40I2G

  • MM# 999ZTC
  • Spec Code SRJ6K
  • Ordering Code 5SGXMB5R1F40I2G
  • Stepping A1
  • MDDS Content IDs 725343

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F40I2G

  • MM# 999ZTF
  • Spec Code SRJ6M
  • Ordering Code 5SGXMB5R2F40I2G
  • Stepping A1
  • MDDS Content IDs 725417

Retired and discontinued

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F40C2L

  • MM# 969076
  • Spec Code SR7M3
  • Ordering Code 5SGXEB5R1F40C2L
  • Stepping A1
  • MDDS Content IDs 694500

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F43C2LN

  • MM# 969078
  • Spec Code SR7M5
  • Ordering Code 5SGXEB5R1F43C2LN
  • Stepping A1
  • MDDS Content IDs 694042

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C3N

  • MM# 969080
  • Spec Code SR7M7
  • Ordering Code 5SGXEB5R2F40C3N
  • Stepping A1
  • MDDS Content IDs 693851

Stratix® V 5SGXB5 FPGA 5SGXEB5R1F43I2N

  • MM# 969081
  • Spec Code SR7M6
  • Ordering Code 5SGXEB5R1F43I2N
  • Stepping A1
  • MDDS Content IDs 696048

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40I3LN

  • MM# 969084
  • Spec Code SR7M8
  • Ordering Code 5SGXEB5R2F40I3LN
  • Stepping A1
  • MDDS Content IDs 698959

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F43I3LN

  • MM# 969086
  • Spec Code SR7MD
  • Ordering Code 5SGXEB5R3F43I3LN
  • Stepping A1
  • MDDS Content IDs 702269

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F43C2N

  • MM# 969253
  • Spec Code SR7SA
  • Ordering Code 5SGXMB5R3F43C2N
  • Stepping A1
  • MDDS Content IDs 699583

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F43I3N

  • MM# 969256
  • Spec Code SR7SB
  • Ordering Code 5SGXMB5R3F43I3N
  • Stepping A1
  • MDDS Content IDs 696596

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40C2N

  • MM# 969356
  • Spec Code SR7VB
  • Ordering Code 5SGXMB5R1F40C2N
  • Stepping A1
  • MDDS Content IDs 699632

Stratix® V 5SGXB5 FPGA 5SGXMB5R1F40I2N

  • MM# 969358
  • Spec Code SR7VC
  • Ordering Code 5SGXMB5R1F40I2N
  • Stepping A1
  • MDDS Content IDs 698529

Stratix® V 5SGXB5 FPGA 5SGXMB5R2F43I3LN

  • MM# 969359
  • Spec Code SR7VE
  • Ordering Code 5SGXMB5R2F43I3LN
  • Stepping A1
  • MDDS Content IDs 701805

Stratix® V 5SGXB5 FPGA 5SGXMB5R3F40C2LN

  • MM# 969362
  • Spec Code SR7VF
  • Ordering Code 5SGXMB5R3F40C2LN
  • Stepping A1
  • MDDS Content IDs 698629

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C2L

  • MM# 970485
  • Spec Code SR8R2
  • Ordering Code 5SGXEB5R2F40C2L
  • Stepping A1
  • MDDS Content IDs 693175

Stratix® V 5SGXB5 FPGA 5SGXEB5R2F40C2LN

  • MM# 970486
  • Spec Code SR8R3
  • Ordering Code 5SGXEB5R2F40C2LN
  • Stepping A1
  • MDDS Content IDs 698144

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C2L

  • MM# 970488
  • Spec Code SR8R5
  • Ordering Code 5SGXEB5R3F40C2L
  • Stepping A1
  • MDDS Content IDs 700445

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F40C3N

  • MM# 970489
  • Spec Code SR8R6
  • Ordering Code 5SGXEB5R3F40C3N
  • Stepping A1
  • MDDS Content IDs 693457

Stratix® V 5SGXB5 FPGA 5SGXEB5R3F43C2LN

  • MM# 970491
  • Spec Code SR8R8
  • Ordering Code 5SGXEB5R3F43C2LN
  • Stepping A1
  • MDDS Content IDs 700625

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN Information

SR7M3

SRHRG

SRHZJ

SRHYS

SRHR7

SRHR6

SRHR3

SRHQ9

SRHQ8

SR8R8

SR8R6

SR8R5

SR8R3

SR8R2

SR7SB

SRHXV

SRJ3P

SR7SA

SRHXU

SRJ3Q

SRHXT

SRJ3R

SRHXS

SRJ00

SRJ01

SRJ3J

SRJ3L

SRHXW

SR7VE

SR7VC

SR7VB

SRJ6K

SRJ6M

SR7VF

SRHWA

SRJ6J

SRJ1W

SRJ1X

SRJ1Y

SRJ1Z

SRHZX

SRHZW

SRHW3

SRHZV

SRHW2

SRHZU

SR7M8

SRHW1

SR7M7

SR7M6

SRJ1T

SR7M5

SR7MD

SRHW9

SRHW8

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Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count†

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers†

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate†

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.

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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.

Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.

Refer to Datasheet for formal definitions of product properties and features.

‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.

“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.