Stratix® V 5SGXB9 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXB9 FPGA 5SGXEB9R1H43C2G

  • MM# 99A1MT
  • Spec Code SRJL5
  • Ordering Code 5SGXEB9R1H43C2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R1H43C2LG

  • MM# 99A1MV
  • Spec Code SRJL6
  • Ordering Code 5SGXEB9R1H43C2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R1H43I2G

  • MM# 99A1MW
  • Spec Code SRJL7
  • Ordering Code 5SGXEB9R1H43I2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R2H43C2G

  • MM# 99A1MX
  • Spec Code SRJL8
  • Ordering Code 5SGXEB9R2H43C2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R2H43C2LG

  • MM# 99A1MZ
  • Spec Code SRJL9
  • Ordering Code 5SGXEB9R2H43C2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R2H43C3G

  • MM# 99A1N0
  • Spec Code SRJLA
  • Ordering Code 5SGXEB9R2H43C3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R2H43I2G

  • MM# 99A1N1
  • Spec Code SRJLB
  • Ordering Code 5SGXEB9R2H43I2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R2H43I2LG

  • MM# 99A1N2
  • Spec Code SRJLC
  • Ordering Code 5SGXEB9R2H43I2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R2H43I3G

  • MM# 99A1N3
  • Spec Code SRJLD
  • Ordering Code 5SGXEB9R2H43I3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R2H43I3LG

  • MM# 99A1N5
  • Spec Code SRJLE
  • Ordering Code 5SGXEB9R2H43I3LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R3H43C2G

  • MM# 99A1N6
  • Spec Code SRJLF
  • Ordering Code 5SGXEB9R3H43C2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R3H43C2LG

  • MM# 99A1N7
  • Spec Code SRJLG
  • Ordering Code 5SGXEB9R3H43C2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R3H43C3G

  • MM# 99A1N8
  • Spec Code SRJLH
  • Ordering Code 5SGXEB9R3H43C3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R3H43C4G

  • MM# 99A1N9
  • Spec Code SRJLJ
  • Ordering Code 5SGXEB9R3H43C4G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R3H43I3G

  • MM# 99A1NA
  • Spec Code SRJLK
  • Ordering Code 5SGXEB9R3H43I3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R3H43I3LG

  • MM# 99A1NC
  • Spec Code SRJLL
  • Ordering Code 5SGXEB9R3H43I3LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXEB9R3H43I4G

  • MM# 99A1ND
  • Spec Code SRJLM
  • Ordering Code 5SGXEB9R3H43I4G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R1H43C2G

  • MM# 99A1TV
  • Spec Code SRJP6
  • Ordering Code 5SGXMB9R1H43C2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R1H43C2LG

  • MM# 99A1TW
  • Spec Code SRJP7
  • Ordering Code 5SGXMB9R1H43C2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R1H43I2G

  • MM# 99A1TX
  • Spec Code SRJP8
  • Ordering Code 5SGXMB9R1H43I2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R2H43C2G

  • MM# 99A1TZ
  • Spec Code SRJP9
  • Ordering Code 5SGXMB9R2H43C2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R2H43C2LG

  • MM# 99A1V0
  • Spec Code SRJPA
  • Ordering Code 5SGXMB9R2H43C2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R2H43C3G

  • MM# 99A1V2
  • Spec Code SRJPB
  • Ordering Code 5SGXMB9R2H43C3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R2H43I2G

  • MM# 99A1V3
  • Spec Code SRJPC
  • Ordering Code 5SGXMB9R2H43I2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R2H43I2LG

  • MM# 99A1V4
  • Spec Code SRJPD
  • Ordering Code 5SGXMB9R2H43I2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R2H43I3G

  • MM# 99A1V5
  • Spec Code SRJPE
  • Ordering Code 5SGXMB9R2H43I3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R3H43C2G

  • MM# 99A1V7
  • Spec Code SRJPG
  • Ordering Code 5SGXMB9R3H43C2G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R3H43C2LG

  • MM# 99A1V8
  • Spec Code SRJPH
  • Ordering Code 5SGXMB9R3H43C2LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R3H43C3G

  • MM# 99A1V9
  • Spec Code SRJPJ
  • Ordering Code 5SGXMB9R3H43C3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R3H43C4G

  • MM# 99A1VA
  • Spec Code SRJPK
  • Ordering Code 5SGXMB9R3H43C4G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R3H43I3G

  • MM# 99A1VC
  • Spec Code SRJPL
  • Ordering Code 5SGXMB9R3H43I3G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R3H43I3LG

  • MM# 99A1VD
  • Spec Code SRJPM
  • Ordering Code 5SGXMB9R3H43I3LG
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R3H43I4G

  • MM# 99A1VG
  • Spec Code SRJPN
  • Ordering Code 5SGXMB9R3H43I4G
  • Stepping A1

Stratix® V 5SGXB9 FPGA 5SGXMB9R2H43I3LG

  • MM# 99A237
  • Spec Code SRJQF
  • Ordering Code 5SGXMB9R2H43I3LG
  • Stepping A1

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SRJL9

SRJPA

SRJPB

SRJPC

SRJPD

SRJP6

SRJP7

SRJP8

SRJL5

SRJP9

SRJL6

SRJL7

SRJL8

SRJQF

SRJPM

SRJLJ

SRJPN

SRJLK

SRJLL

SRJLM

SRJLA

SRJPE

SRJLB

SRJLC

SRJPG

SRJLD

SRJPH

SRJLE

SRJLF

SRJPJ

SRJLG

SRJPK

SRJLH

SRJPL

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.