Stratix® V 5SGXAB FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXAB FPGA 5SGXEABK1H40C2G

  • MM# 99A1L8
  • Spec Code SRJK1
  • Ordering Code 5SGXEABK1H40C2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABK1H40I2G

  • MM# 99A1LA
  • Spec Code SRJK3
  • Ordering Code 5SGXEABK1H40I2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABK2H40C2G

  • MM# 99A1LC
  • Spec Code SRJK4
  • Ordering Code 5SGXEABK2H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK2H40C3G

  • MM# 99A1LF
  • Spec Code SRJK6
  • Ordering Code 5SGXEABK2H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK2H40I2G

  • MM# 99A1LG
  • Spec Code SRJK7
  • Ordering Code 5SGXEABK2H40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK2H40I3G

  • MM# 99A1LL
  • Spec Code SRJKA
  • Ordering Code 5SGXEABK2H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK3H40C2G

  • MM# 99A1LP
  • Spec Code SRJKC
  • Ordering Code 5SGXEABK3H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK3H40C3G

  • MM# 99A1LT
  • Spec Code SRJKE
  • Ordering Code 5SGXEABK3H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK3H40C4G

  • MM# 99A1LV
  • Spec Code SRJKF
  • Ordering Code 5SGXEABK3H40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK3H40I3G

  • MM# 99A1LW
  • Spec Code SRJKG
  • Ordering Code 5SGXEABK3H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABK3H40I4G

  • MM# 99A1M0
  • Spec Code SRJKJ
  • Ordering Code 5SGXEABK3H40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXEABN1F45C2G

  • MM# 99A1M1
  • Spec Code SRJKK
  • Ordering Code 5SGXEABN1F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN1F45I2G

  • MM# 99A1M3
  • Spec Code SRJKM
  • Ordering Code 5SGXEABN1F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN2F45C2G

  • MM# 99A1M4
  • Spec Code SRJKN
  • Ordering Code 5SGXEABN2F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN2F45C3G

  • MM# 99A1M6
  • Spec Code SRJKQ
  • Ordering Code 5SGXEABN2F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN2F45I2G

  • MM# 99A1M7
  • Spec Code SRJKR
  • Ordering Code 5SGXEABN2F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN2F45I3G

  • MM# 99A1M9
  • Spec Code SRJKT
  • Ordering Code 5SGXEABN2F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN2F46C2G

  • MM# 99A1MD
  • Spec Code SRJKV
  • Ordering Code 5SGXEABN2F46C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN3F45C2G

  • MM# 99A1MG
  • Spec Code SRJKX
  • Ordering Code 5SGXEABN3F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN3F45C3G

  • MM# 99A1MJ
  • Spec Code SRJKZ
  • Ordering Code 5SGXEABN3F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN3F45C4G

  • MM# 99A1MK
  • Spec Code SRJL0
  • Ordering Code 5SGXEABN3F45C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN3F45I3G

  • MM# 99A1ML
  • Spec Code SRJL1
  • Ordering Code 5SGXEABN3F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXEABN3F45I4G

  • MM# 99A1MN
  • Spec Code SRJL3
  • Ordering Code 5SGXEABN3F45I4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABK1H40C2G

  • MM# 99A1RG
  • Spec Code SRJN5
  • Ordering Code 5SGXMABK1H40C2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABK1H40I2G

  • MM# 99A1RJ
  • Spec Code SRJN7
  • Ordering Code 5SGXMABK1H40I2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABK2H40C2G

  • MM# 99A1RK
  • Spec Code SRJN8
  • Ordering Code 5SGXMABK2H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK2H40C3G

  • MM# 99A1RM
  • Spec Code SRJNA
  • Ordering Code 5SGXMABK2H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK2H40I2G

  • MM# 99A1RN
  • Spec Code SRJNB
  • Ordering Code 5SGXMABK2H40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK2H40I3G

  • MM# 99A1RR
  • Spec Code SRJND
  • Ordering Code 5SGXMABK2H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK3H40C2G

  • MM# 99A1RW
  • Spec Code SRJNF
  • Ordering Code 5SGXMABK3H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK3H40C3G

  • MM# 99A1RZ
  • Spec Code SRJNH
  • Ordering Code 5SGXMABK3H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK3H40C4G

  • MM# 99A1T0
  • Spec Code SRJNJ
  • Ordering Code 5SGXMABK3H40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK3H40I3G

  • MM# 99A1T1
  • Spec Code SRJNK
  • Ordering Code 5SGXMABK3H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABK3H40I4G

  • MM# 99A1T3
  • Spec Code SRJNM
  • Ordering Code 5SGXMABK3H40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXAB FPGA 5SGXMABN1F45C2G

  • MM# 99A1T4
  • Spec Code SRJNN
  • Ordering Code 5SGXMABN1F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN1F45I2G

  • MM# 99A1T6
  • Spec Code SRJNQ
  • Ordering Code 5SGXMABN1F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN2F45C2G

  • MM# 99A1T9
  • Spec Code SRJNS
  • Ordering Code 5SGXMABN2F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN2F45C3G

  • MM# 99A1TC
  • Spec Code SRJNU
  • Ordering Code 5SGXMABN2F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN2F45I2G

  • MM# 99A1TD
  • Spec Code SRJNV
  • Ordering Code 5SGXMABN2F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN2F45I3G

  • MM# 99A1TG
  • Spec Code SRJNX
  • Ordering Code 5SGXMABN2F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN3F45C2G

  • MM# 99A1TJ
  • Spec Code SRJNZ
  • Ordering Code 5SGXMABN3F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN3F45C3G

  • MM# 99A1TM
  • Spec Code SRJP1
  • Ordering Code 5SGXMABN3F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN3F45C4G

  • MM# 99A1TN
  • Spec Code SRJP2
  • Ordering Code 5SGXMABN3F45C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN3F45I3G

  • MM# 99A1TP
  • Spec Code SRJP3
  • Ordering Code 5SGXMABN3F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXAB FPGA 5SGXMABN3F45I4G

  • MM# 99A1TT
  • Spec Code SRJP5
  • Ordering Code 5SGXMABN3F45I4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN/MDDS Information

SRJKX

SRJKZ

SRJNA

SRJNB

SRJL1

SRJP5

SRJKQ

SRJKR

SRJL3

SRJN5

SRJKT

SRJN7

SRJN8

SRJKV

SRJKJ

SRJKK

SRJP1

SRJKM

SRJP2

SRJKN

SRJP3

SRJL0

SRJKA

SRJKC

SRJKE

SRJKF

SRJKG

SRJNS

SRJK1

SRJNU

SRJK3

SRJNV

SRJK4

SRJNX

SRJK6

SRJK7

SRJNZ

SRJNK

SRJNM

SRJNN

SRJNQ

SRJND

SRJNF

SRJNH

SRJNJ

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.