Stratix® V 5SGXAB FPGA
Specifications
Compare Intel® Products
Essentials
-
Product Collection
Stratix® V GX FPGA
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Marketing Status
Launched
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Launch Date
2010
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Lithography
28 nm
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Resources
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Logic Elements (LE)
952000
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Adaptive Logic Modules (ALM)
359200
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Adaptive Logic Module (ALM) Registers
1436800
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Fabric and I/O Phase-Locked Loops (PLLs)
28
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Maximum Embedded Memory
62.96 Mb
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Digital Signal Processing (DSP) Blocks
352
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP)
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Hard Memory Controllers
No
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External Memory Interfaces (EMIF)
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3
I/O Specifications
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Maximum User I/O Count†
840
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS
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Maximum LVDS Pairs
420
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Maximum Non-Return to Zero (NRZ) Transceivers†
48
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Maximum Non-Return to Zero (NRZ) Data Rate†
14.1 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Package Specifications
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Package Options
F1517, F1932
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Stratix® V 5SGXAB FPGA 5SGXEABN2F46C2G
- MM# 99A1MD
- Spec Code SRJKV
- Ordering Code 5SGXEABN2F46C2G
- Stepping A1
- ECCN 3A001.A.7.A
- CCATS G171972
Retired and discontinued
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SRJNA
- 99A1RM PCN
SRJNB
- 99A1RN PCN
SR8FL
- 970142 PCN
SR8FJ
- 970140 PCN
SRJN5
- 99A1RG PCN
SR7M1
- 969074 PCN
SRJN6
- 99A1RH PCN
SR7M0
- 969073 PCN
SRJN7
- 99A1RJ PCN
SRJN8
- 99A1RK PCN
SRJN9
- 99A1RL PCN
SRJKX
- 99A1MG PCN
SR7S1
- 969245 PCN
SRJKY
- 99A1MH PCN
SRJKZ
- 99A1MJ PCN
SRJKP
- 99A1M5 PCN
SRJL1
- 99A1ML PCN
SRJP5
- 99A1TT PCN
SRJKQ
- 99A1M6 PCN
SRJL2
- 99A1MM PCN
SRJKR
- 99A1M7 PCN
SRJL3
- 99A1MN PCN
SRJKS
- 99A1M8 PCN
SR7S6
- 969249 PCN
SRJKT
- 99A1M9 PCN
SRJKU
- 99A1MC PCN
SR7S4
- 969247 PCN
SRJKV
- 99A1MD PCN
SR7S3
- 969246 PCN
SRJKH
- 99A1LX PCN
SRJKJ
- 99A1M0 PCN
SRJKK
- 99A1M1 PCN
SRJP0
- 99A1TK PCN
SR7VA
- 969355 PCN
SRJKL
- 99A1M2 PCN
SRJP1
- 99A1TM PCN
SRJKM
- 99A1M3 PCN
SRJP2
- 99A1TN PCN
SRJKN
- 99A1M4 PCN
SRJP3
- 99A1TP PCN
SRJL0
- 99A1MK PCN
SRJP4
- 99A1TR PCN
SRJKA
- 99A1LL PCN
SRJKB
- 99A1LN PCN
SRJKC
- 99A1LP PCN
SRJKD
- 99A1LR PCN
SRJKE
- 99A1LT PCN
SRJKF
- 99A1LV PCN
SRJKG
- 99A1LW PCN
SR7V5
- 969353 PCN
SRJK9
- 99A1LK PCN
SRJNS
- 99A1T9 PCN
SRJK1
- 99A1L8 PCN
SRJNT
- 99A1TA PCN
SRJK2
- 99A1L9 PCN
SRJNU
- 99A1TC PCN
SRJK3
- 99A1LA PCN
SRJNV
- 99A1TD PCN
SR7V9
- 969357 PCN
SRJK4
- 99A1LC PCN
SRJNW
- 99A1TF PCN
SRJK5
- 99A1LD PCN
SRJNX
- 99A1TG PCN
SR7V7
- 969352 PCN
SRJK6
- 99A1LF PCN
SRJNY
- 99A1TH PCN
SRJK7
- 99A1LG PCN
SRJNZ
- 99A1TJ PCN
SRJNK
- 99A1T1 PCN
SRJNL
- 99A1T2 PCN
SRJNM
- 99A1T3 PCN
SR7LX
- 969070 PCN
SR8FQ
- 970146 PCN
SRJNN
- 99A1T4 PCN
SR8FP
- 970145 PCN
SR7LV
- 969068 PCN
SRJNP
- 99A1T5 PCN
SR8FN
- 970144 PCN
SRJNQ
- 99A1T6 PCN
SR8FM
- 970143 PCN
SRJNR
- 99A1T8 PCN
SRJNC
- 99A1RP PCN
SRJND
- 99A1RR PCN
SRJNE
- 99A1RT PCN
SRJNF
- 99A1RW PCN
SRJNG
- 99A1RX PCN
SRJNH
- 99A1RZ PCN
SRJNJ
- 99A1T0 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.