Stratix® V 5SGXA9 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXA9 FPGA 5SGXEA9K1H40C2G

  • MM# 99A1JW
  • Spec Code SRJJ1
  • Ordering Code 5SGXEA9K1H40C2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9K1H40I2G

  • MM# 99A1JZ
  • Spec Code SRJJ3
  • Ordering Code 5SGXEA9K1H40I2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9K2H40C2G

  • MM# 99A1K1
  • Spec Code SRJJ4
  • Ordering Code 5SGXEA9K2H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K2H40C3G

  • MM# 99A1K3
  • Spec Code SRJJ6
  • Ordering Code 5SGXEA9K2H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K2H40I2G

  • MM# 99A1K5
  • Spec Code SRJJ7
  • Ordering Code 5SGXEA9K2H40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K2H40I3G

  • MM# 99A1K7
  • Spec Code SRJJ9
  • Ordering Code 5SGXEA9K2H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K3H40C2G

  • MM# 99A1K9
  • Spec Code SRJJB
  • Ordering Code 5SGXEA9K3H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K3H40C3G

  • MM# 99A1KD
  • Spec Code SRJJD
  • Ordering Code 5SGXEA9K3H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K3H40C4G

  • MM# 99A1KF
  • Spec Code SRJJE
  • Ordering Code 5SGXEA9K3H40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K3H40I3G

  • MM# 99A1KG
  • Spec Code SRJJF
  • Ordering Code 5SGXEA9K3H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9K3H40I4G

  • MM# 99A1KJ
  • Spec Code SRJJH
  • Ordering Code 5SGXEA9K3H40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXEA9N1F45C2G

  • MM# 99A1KK
  • Spec Code SRJJJ
  • Ordering Code 5SGXEA9N1F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N1F45I2G

  • MM# 99A1KM
  • Spec Code SRJJL
  • Ordering Code 5SGXEA9N1F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N2F45C2G

  • MM# 99A1KN
  • Spec Code SRJJM
  • Ordering Code 5SGXEA9N2F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N2F45C3G

  • MM# 99A1KT
  • Spec Code SRJJP
  • Ordering Code 5SGXEA9N2F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N2F45I2G

  • MM# 99A1KV
  • Spec Code SRJJQ
  • Ordering Code 5SGXEA9N2F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N2F45I3G

  • MM# 99A1KX
  • Spec Code SRJJS
  • Ordering Code 5SGXEA9N2F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N3F45C2G

  • MM# 99A1L0
  • Spec Code SRJJU
  • Ordering Code 5SGXEA9N3F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N3F45C3G

  • MM# 99A1L2
  • Spec Code SRJJW
  • Ordering Code 5SGXEA9N3F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N3F45C4G

  • MM# 99A1L3
  • Spec Code SRJJX
  • Ordering Code 5SGXEA9N3F45C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N3F45I3G

  • MM# 99A1L4
  • Spec Code SRJJY
  • Ordering Code 5SGXEA9N3F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXEA9N3F45I4G

  • MM# 99A1L7
  • Spec Code SRJK0
  • Ordering Code 5SGXEA9N3F45I4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9K1H40C2G

  • MM# 99A1P4
  • Spec Code SRJM5
  • Ordering Code 5SGXMA9K1H40C2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9K1H40I2G

  • MM# 99A1P6
  • Spec Code SRJM7
  • Ordering Code 5SGXMA9K1H40I2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9K2H40C2G

  • MM# 99A1P7
  • Spec Code SRJM8
  • Ordering Code 5SGXMA9K2H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K2H40C3G

  • MM# 99A1PA
  • Spec Code SRJMA
  • Ordering Code 5SGXMA9K2H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K2H40I2G

  • MM# 99A1PC
  • Spec Code SRJMB
  • Ordering Code 5SGXMA9K2H40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K2H40I3G

  • MM# 99A1PF
  • Spec Code SRJMD
  • Ordering Code 5SGXMA9K2H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K3H40C2G

  • MM# 99A1PH
  • Spec Code SRJMF
  • Ordering Code 5SGXMA9K3H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K3H40C3G

  • MM# 99A1PK
  • Spec Code SRJMH
  • Ordering Code 5SGXMA9K3H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K3H40C4G

  • MM# 99A1PL
  • Spec Code SRJMJ
  • Ordering Code 5SGXMA9K3H40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K3H40I3G

  • MM# 99A1PN
  • Spec Code SRJMK
  • Ordering Code 5SGXMA9K3H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9K3H40I4G

  • MM# 99A1PR
  • Spec Code SRJMM
  • Ordering Code 5SGXMA9K3H40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGXA9 FPGA 5SGXMA9N1F45C2G

  • MM# 99A1PT
  • Spec Code SRJMN
  • Ordering Code 5SGXMA9N1F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N1F45I2G

  • MM# 99A1PW
  • Spec Code SRJMQ
  • Ordering Code 5SGXMA9N1F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N2F45C2G

  • MM# 99A1PX
  • Spec Code SRJMR
  • Ordering Code 5SGXMA9N2F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N2F45C3G

  • MM# 99A1R0
  • Spec Code SRJMT
  • Ordering Code 5SGXMA9N2F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N2F45I2G

  • MM# 99A1R1
  • Spec Code SRJMU
  • Ordering Code 5SGXMA9N2F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N2F45I3G

  • MM# 99A1R4
  • Spec Code SRJMW
  • Ordering Code 5SGXMA9N2F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N3F45C2G

  • MM# 99A1R6
  • Spec Code SRJMY
  • Ordering Code 5SGXMA9N3F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N3F45C3G

  • MM# 99A1R8
  • Spec Code SRJN0
  • Ordering Code 5SGXMA9N3F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N3F45C4G

  • MM# 99A1R9
  • Spec Code SRJN1
  • Ordering Code 5SGXMA9N3F45C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N3F45I3G

  • MM# 99A1RA
  • Spec Code SRJN2
  • Ordering Code 5SGXMA9N3F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SGXA9 FPGA 5SGXMA9N3F45I4G

  • MM# 99A1RD
  • Spec Code SRJN4
  • Ordering Code 5SGXMA9N3F45I4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN/MDDS Information

SRJJ7

SRJJ9

SRJMR

SRJN4

SRJJ1

SRJMT

SRJMU

SRJJ3

SRJJ4

SRJMW

SRJJ6

SRJMY

SRJMJ

SRJMK

SRJMM

SRJMN

SRJN0

SRJN1

SRJMQ

SRJN2

SRJMB

SRJMD

SRJMF

SRJMH

SRJJW

SRJJX

SRJJY

SRJMA

SRJK0

SRJJP

SRJJQ

SRJM5

SRJJS

SRJM7

SRJJU

SRJM8

SRJJH

SRJJJ

SRJJL

SRJJM

SRJJB

SRJJD

SRJJE

SRJJF

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.