Stratix® V 5SGXB6 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40I2G

  • MM# 999Z2A
  • Spec Code SRHR9
  • Ordering Code 5SGXEB6R1F40I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C2G

  • MM# 999Z2D
  • Spec Code SRHRA
  • Ordering Code 5SGXEB6R2F40C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I2LG

  • MM# 999Z2F
  • Spec Code SRHRB
  • Ordering Code 5SGXEB6R2F40I2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F43C1G

  • MM# 999Z2R
  • Spec Code SRHRK
  • Ordering Code 5SGXEB6R1F43C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F43C2G

  • MM# 999Z2T
  • Spec Code SRHRL
  • Ordering Code 5SGXEB6R1F43C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43C2G

  • MM# 999Z2V
  • Spec Code SRHRM
  • Ordering Code 5SGXEB6R2F43C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C3G

  • MM# 999Z2W
  • Spec Code SRHRN
  • Ordering Code 5SGXEB6R3F40C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F43C4G

  • MM# 999Z2X
  • Spec Code SRHRP
  • Ordering Code 5SGXEB6R3F43C4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F43I4G

  • MM# 999Z2Z
  • Spec Code SRHRQ
  • Ordering Code 5SGXEB6R3F43I4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C2LG

  • MM# 999Z36
  • Spec Code SRHRW
  • Ordering Code 5SGXEB6R2F40C2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I2G

  • MM# 999Z37
  • Spec Code SRHRX
  • Ordering Code 5SGXEB6R2F40I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I3G

  • MM# 999Z38
  • Spec Code SRHRY
  • Ordering Code 5SGXEB6R2F40I3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I3LG

  • MM# 999Z39
  • Spec Code SRHRZ
  • Ordering Code 5SGXEB6R2F40I3LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43C3G

  • MM# 999Z3A
  • Spec Code SRHS0
  • Ordering Code 5SGXEB6R2F43C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C2G

  • MM# 999Z3C
  • Spec Code SRHS1
  • Ordering Code 5SGXEB6R3F40C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C2LG

  • MM# 999Z3D
  • Spec Code SRHS2
  • Ordering Code 5SGXEB6R3F40C2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40I4G

  • MM# 999Z3F
  • Spec Code SRHS3
  • Ordering Code 5SGXEB6R3F40I4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F43I3G

  • MM# 999Z3G
  • Spec Code SRHS4
  • Ordering Code 5SGXEB6R3F43I3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40C2G

  • MM# 999Z9R
  • Spec Code SRHWD
  • Ordering Code 5SGXEB6R1F40C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40C2LG

  • MM# 999Z9T
  • Spec Code SRHWE
  • Ordering Code 5SGXEB6R1F40C2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F43I2G

  • MM# 999Z9X
  • Spec Code SRHWH
  • Ordering Code 5SGXEB6R1F43I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C1G

  • MM# 999Z9Z
  • Spec Code SRHWJ
  • Ordering Code 5SGXEB6R2F40C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C3G

  • MM# 999ZA0
  • Spec Code SRHWK
  • Ordering Code 5SGXEB6R2F40C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C4G

  • MM# 999ZA1
  • Spec Code SRHWL
  • Ordering Code 5SGXEB6R3F40C4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40I3G

  • MM# 999ZA2
  • Spec Code SRHWM
  • Ordering Code 5SGXEB6R3F40I3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F43C3G

  • MM# 999ZA3
  • Spec Code SRHWN
  • Ordering Code 5SGXEB6R3F43C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40C2LG

  • MM# 999ZF4
  • Spec Code SRHYV
  • Ordering Code 5SGXMB6R1F40C2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C2LG

  • MM# 999ZF6
  • Spec Code SRHYX
  • Ordering Code 5SGXMB6R2F40C2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F43C1G

  • MM# 999ZF7
  • Spec Code SRHYY
  • Ordering Code 5SGXMB6R2F43C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C3G

  • MM# 999ZFG
  • Spec Code SRHZ4
  • Ordering Code 5SGXMB6R3F40C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40C2G

  • MM# 999ZKD
  • Spec Code SRJ22
  • Ordering Code 5SGXMB6R1F40C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F43I2G

  • MM# 999ZKF
  • Spec Code SRJ23
  • Ordering Code 5SGXMB6R1F43I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I2LG

  • MM# 999ZKK
  • Spec Code SRJ27
  • Ordering Code 5SGXMB6R2F40I2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F43I3G

  • MM# 999ZKN
  • Spec Code SRJ2A
  • Ordering Code 5SGXMB6R2F43I3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C2G

  • MM# 999ZKP
  • Spec Code SRJ2B
  • Ordering Code 5SGXMB6R3F40C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F43C2G

  • MM# 999ZKT
  • Spec Code SRJ2C
  • Ordering Code 5SGXMB6R3F43C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F43C4G

  • MM# 999ZKV
  • Spec Code SRJ2D
  • Ordering Code 5SGXMB6R3F43C4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F43I4G

  • MM# 999ZKW
  • Spec Code SRJ2E
  • Ordering Code 5SGXMB6R3F43I4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40C1G

  • MM# 999ZKZ
  • Spec Code SRJ2G
  • Ordering Code 5SGXEB6R1F40C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43C1G

  • MM# 999ZL0
  • Spec Code SRJ2H
  • Ordering Code 5SGXEB6R2F43C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43I2G

  • MM# 999ZL2
  • Spec Code SRJ2K
  • Ordering Code 5SGXEB6R2F43I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43I3G

  • MM# 999ZL4
  • Spec Code SRJ2M
  • Ordering Code 5SGXEB6R2F43I3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40I3LG

  • MM# 999ZL6
  • Spec Code SRJ2P
  • Ordering Code 5SGXEB6R3F40I3LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F43C2G

  • MM# 999ZLK
  • Spec Code SRJ2Z
  • Ordering Code 5SGXEB6R3F43C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40I2G

  • MM# 999ZMP
  • Spec Code SRJ3U
  • Ordering Code 5SGXMB6R1F40I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40I2LG

  • MM# 999ZMR
  • Spec Code SRJ3V
  • Ordering Code 5SGXMB6R1F40I2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F43C1G

  • MM# 999ZMT
  • Spec Code SRJ3W
  • Ordering Code 5SGXMB6R1F43C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F43C2G

  • MM# 999ZMV
  • Spec Code SRJ3X
  • Ordering Code 5SGXMB6R1F43C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C1G

  • MM# 999ZMW
  • Spec Code SRJ3Y
  • Ordering Code 5SGXMB6R2F40C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C2G

  • MM# 999ZMX
  • Spec Code SRJ3Z
  • Ordering Code 5SGXMB6R2F40C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I3LG

  • MM# 999ZMZ
  • Spec Code SRJ40
  • Ordering Code 5SGXMB6R2F40I3LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C2LG

  • MM# 999ZNA
  • Spec Code SRJ4A
  • Ordering Code 5SGXMB6R3F40C2LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C4G

  • MM# 999ZNC
  • Spec Code SRJ4B
  • Ordering Code 5SGXMB6R3F40C4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40I3G

  • MM# 999ZND
  • Spec Code SRJ4C
  • Ordering Code 5SGXMB6R3F40I3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40I3LG

  • MM# 999ZNG
  • Spec Code SRJ4D
  • Ordering Code 5SGXMB6R3F40I3LG
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F43C3G

  • MM# 999ZNJ
  • Spec Code SRJ4F
  • Ordering Code 5SGXMB6R3F43C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40C1G

  • MM# 999ZTL
  • Spec Code SRJ6R
  • Ordering Code 5SGXMB6R1F40C1G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C3G

  • MM# 999ZTM
  • Spec Code SRJ6S
  • Ordering Code 5SGXMB6R2F40C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I2G

  • MM# 999ZTN
  • Spec Code SRJ6T
  • Ordering Code 5SGXMB6R2F40I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I3G

  • MM# 999ZTP
  • Spec Code SRJ6U
  • Ordering Code 5SGXMB6R2F40I3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F43C2G

  • MM# 999ZTR
  • Spec Code SRJ6V
  • Ordering Code 5SGXMB6R2F43C2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F43C3G

  • MM# 999ZTT
  • Spec Code SRJ6W
  • Ordering Code 5SGXMB6R2F43C3G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F43I2G

  • MM# 999ZTV
  • Spec Code SRJ6X
  • Ordering Code 5SGXMB6R2F43I2G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40I4G

  • MM# 999ZTX
  • Spec Code SRJ6Z
  • Ordering Code 5SGXMB6R3F40I4G
  • Stepping A1

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F43I3G

  • MM# 999ZTZ
  • Spec Code SRJ70
  • Ordering Code 5SGXMB6R3F43I3G
  • Stepping A1

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SRHR9

SRHRB

SRHRA

SRHYV

SRHZ4

SRHYY

SRHYX

SRJ4A

SRJ4B

SRJ4C

SRJ4D

SRJ4F

SRJ3X

SRJ3Y

SRJ3Z

SRJ3U

SRJ3V

SRJ3W

SRJ40

SRJ2Z

SRJ6S

SRJ2P

SRJ6T

SRJ6U

SRJ6V

SRJ6W

SRJ6X

SRHWN

SRJ6Z

SRJ2G

SRJ2H

SRJ2K

SRJ70

SRJ2M

SRJ6R

SRHWE

SRHWD

SRJ2A

SRJ2B

SRJ2C

SRJ2D

SRHRZ

SRJ2E

SRHRY

SRHWM

SRJ27

SRHWL

SRHWK

SRHWJ

SRHWH

SRHRP

SRHS1

SRHS0

SRHRN

SRHRM

SRJ22

SRHRL

SRJ23

SRHRK

SRHRX

SRHRW

SRHS4

SRHS3

SRHRQ

SRHS2

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.