Stratix® V 5SGXBB FPGA
Specifications
Compare Intel® Products
Essentials
-
Product Collection
Stratix® V GX FPGA
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Marketing Status
Launched
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Launch Date
2010
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Lithography
28 nm
Resources
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Logic Elements (LE)
952000
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Adaptive Logic Modules (ALM)
359200
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Adaptive Logic Module (ALM) Registers
1436800
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Fabric and I/O Phase-Locked Loops (PLLs)
32
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Maximum Embedded Memory
62.96 Mb
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Digital Signal Processing (DSP) Blocks
352
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP)
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Hard Memory Controllers
No
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External Memory Interfaces (EMIF)
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3
I/O Specifications
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Maximum User I/O Count†
600
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS
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Maximum LVDS Pairs
300
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Maximum Non-Return to Zero (NRZ) Transceivers†
66
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Maximum Non-Return to Zero (NRZ) Data Rate†
14.1 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Package Specifications
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Package Options
F1760
Supplemental Information
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Datasheet
Datasheet Group
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Additional Information
Product Table
Ordering and Compliance
Ordering and spec information
Retired and discontinued
Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I2N
- MM# 972575
- Spec Code SRAP4
- Ordering Code 5SGXMBBR2H40I2N
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I3N
- MM# 972576
- Spec Code SRAP5
- Ordering Code 5SGXMBBR2H40I3N
- Stepping A1
Trade compliance information
- ECCN 3A001.A.7.B
- CCATS G171972
- US HTS 8542390001
PCN Information
SR8RL
- 970503 PCN
SRAP5
- 972576 PCN
SRAP4
- 972575 PCN
SR7PD
- 969154 PCN
SR7PC
- 969155 PCN
SR7PB
- 969152 PCN
SRAP8
- 972579 PCN
SR7PA
- 969153 PCN
SRAP6
- 972577 PCN
SRJLY
- 99A1NV PCN
SRJLZ
- 99A1NX PCN
SR52Q
- 966066 PCN
SR52P
- 966065 PCN
SR52N
- 966064 PCN
SR52M
- 966063 PCN
SR52L
- 966062 PCN
SRJLQ
- 99A1NJ PCN
SRJM2
- 99A1P1 PCN
SRJPU
- 99A1VN PCN
SRJQ6
- 99A1W4 PCN
SRJLR
- 99A1NK PCN
SRJM3
- 99A1P2 PCN
SRJPV
- 99A1VP PCN
SRJQ7
- 99A1W5 PCN
SRJLS
- 99A1NL PCN
SRJM4
- 99A1P3 PCN
SRJPW
- 99A1VR PCN
SRJLT
- 99A1NM PCN
SRJPX
- 99A1VT PCN
SRJQ9
- 99A1W6 PCN
SRJLU
- 99A1NN PCN
SRJPY
- 99A1VW PCN
SRJLV
- 99A1NP PCN
SRJPZ
- 99A1VX PCN
SRJLW
- 99A1NR PCN
SRJLX
- 99A1NT PCN
SRBTX
- 973972 PCN
SRJQ0
- 99A1VZ PCN
SR9WA
- 972252 PCN
SRJPP
- 99A1VH PCN
SRJQ1
- 99A1W0 PCN
SRJPQ
- 99A1VJ PCN
SRJQ2
- 99A1W1 PCN
SRJLN
- 99A1NF PCN
SRJPR
- 99A1VK PCN
SRJQ3
- 99A1W2 PCN
SRJM0
- 99A1NZ PCN
SRJPS
- 99A1VL PCN
SRJLP
- 99A1NH PCN
SRJM1
- 99A1P0 PCN
SRJPT
- 99A1VM PCN
SRJQ5
- 99A1W3 PCN
SRBTZ
- 973974 PCN
SR7VS
- 969371 PCN
SR7VR
- 969372 PCN
SR7VQ
- 969370 PCN
SR7VP
- 969368 PCN
SR7VN
- 969367 PCN
SRBU0
- 973977 PCN
SRA61
- 971530 PCN
SRA60
- 971529 PCN
SRJH0
- 99A1HF PCN
SR7VM
- 969369 PCN
SR91F
- 970839 PCN
SR91E
- 970838 PCN
SR5EH
- 966488 PCN
SR5EG
- 966487 PCN
SRC8C
- 974140 PCN
SRC8B
- 974139 PCN
SR78M
- 968649 PCN
SR78L
- 968648 PCN
SR78K
- 968647 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
Give Feedback
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.