Stratix® V 5SGXBB FPGA
Specifications
Compare Intel® Products
Essentials
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Product Collection
Stratix® V GX FPGA
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Status
Launched
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Launch Date
2010
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Lithography
28 nm
Resources
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Logic Elements (LE)
952000
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Adaptive Logic Modules (ALM)
359200
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Adaptive Logic Module (ALM) Registers
1436800
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Fabric and I/O Phase-Locked Loops (PLLs)
32
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Maximum Embedded Memory
62.96 Mb
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Digital Signal Processing (DSP) Blocks
352
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP)
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Hard Memory Controllers
No
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External Memory Interfaces (EMIF)
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3
I/O Specifications
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Maximum User I/O Count†
600
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS
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Maximum LVDS Pairs
300
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Maximum Non-Return to Zero (NRZ) Transceivers†
66
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Maximum Non-Return to Zero (NRZ) Data Rate†
14.1 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Package Specifications
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Package Options
F1760
Supplemental Information
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Additional Information
View now
Ordering and Compliance
Ordering and spec information
Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C3G
- MM# 99A1HF
- Spec Code SRJH0
- Ordering Code 5SGXMBBR3H43C3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR1H43C2G
- MM# 99A1NF
- Spec Code SRJLN
- Ordering Code 5SGXEBBR1H43C2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR1H43C2LG
- MM# 99A1NH
- Spec Code SRJLP
- Ordering Code 5SGXEBBR1H43C2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR1H43I2G
- MM# 99A1NJ
- Spec Code SRJLQ
- Ordering Code 5SGXEBBR1H43I2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR2H43C2G
- MM# 99A1NK
- Spec Code SRJLR
- Ordering Code 5SGXEBBR2H43C2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR2H43C2LG
- MM# 99A1NL
- Spec Code SRJLS
- Ordering Code 5SGXEBBR2H43C2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR2H43C3G
- MM# 99A1NM
- Spec Code SRJLT
- Ordering Code 5SGXEBBR2H43C3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I2G
- MM# 99A1NN
- Spec Code SRJLU
- Ordering Code 5SGXEBBR2H43I2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I2LG
- MM# 99A1NP
- Spec Code SRJLV
- Ordering Code 5SGXEBBR2H43I2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I3G
- MM# 99A1NR
- Spec Code SRJLW
- Ordering Code 5SGXEBBR2H43I3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I3LG
- MM# 99A1NT
- Spec Code SRJLX
- Ordering Code 5SGXEBBR2H43I3LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C2G
- MM# 99A1NV
- Spec Code SRJLY
- Ordering Code 5SGXEBBR3H43C2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C2LG
- MM# 99A1NX
- Spec Code SRJLZ
- Ordering Code 5SGXEBBR3H43C2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C3G
- MM# 99A1NZ
- Spec Code SRJM0
- Ordering Code 5SGXEBBR3H43C3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C4G
- MM# 99A1P0
- Spec Code SRJM1
- Ordering Code 5SGXEBBR3H43C4G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR3H43I3G
- MM# 99A1P1
- Spec Code SRJM2
- Ordering Code 5SGXEBBR3H43I3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR3H43I3LG
- MM# 99A1P2
- Spec Code SRJM3
- Ordering Code 5SGXEBBR3H43I3LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXEBBR3H43I4G
- MM# 99A1P3
- Spec Code SRJM4
- Ordering Code 5SGXEBBR3H43I4G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR1H43C2G
- MM# 99A1VH
- Spec Code SRJPP
- Ordering Code 5SGXMBBR1H43C2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR1H43C2LG
- MM# 99A1VJ
- Spec Code SRJPQ
- Ordering Code 5SGXMBBR1H43C2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR1H43I2G
- MM# 99A1VK
- Spec Code SRJPR
- Ordering Code 5SGXMBBR1H43I2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I2G
- MM# 99A1VL
- Spec Code SRJPS
- Ordering Code 5SGXMBBR2H40I2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I2LG
- MM# 99A1VM
- Spec Code SRJPT
- Ordering Code 5SGXMBBR2H40I2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I3G
- MM# 99A1VN
- Spec Code SRJPU
- Ordering Code 5SGXMBBR2H40I3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H43C2G
- MM# 99A1VP
- Spec Code SRJPV
- Ordering Code 5SGXMBBR2H43C2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H43C2LG
- MM# 99A1VR
- Spec Code SRJPW
- Ordering Code 5SGXMBBR2H43C2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H43C3G
- MM# 99A1VT
- Spec Code SRJPX
- Ordering Code 5SGXMBBR2H43C3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I2G
- MM# 99A1VW
- Spec Code SRJPY
- Ordering Code 5SGXMBBR2H43I2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I2LG
- MM# 99A1VX
- Spec Code SRJPZ
- Ordering Code 5SGXMBBR2H43I2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I3G
- MM# 99A1VZ
- Spec Code SRJQ0
- Ordering Code 5SGXMBBR2H43I3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I3LG
- MM# 99A1W0
- Spec Code SRJQ1
- Ordering Code 5SGXMBBR2H43I3LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C2G
- MM# 99A1W1
- Spec Code SRJQ2
- Ordering Code 5SGXMBBR3H43C2G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C2LG
- MM# 99A1W2
- Spec Code SRJQ3
- Ordering Code 5SGXMBBR3H43C2LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C4G
- MM# 99A1W3
- Spec Code SRJQ5
- Ordering Code 5SGXMBBR3H43C4G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR3H43I3G
- MM# 99A1W4
- Spec Code SRJQ6
- Ordering Code 5SGXMBBR3H43I3G
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR3H43I3LG
- MM# 99A1W5
- Spec Code SRJQ7
- Ordering Code 5SGXMBBR3H43I3LG
- Stepping A1
Stratix® V 5SGXBB FPGA 5SGXMBBR3H43I4G
- MM# 99A1W6
- Spec Code SRJQ9
- Ordering Code 5SGXMBBR3H43I4G
- Stepping A1
Trade compliance information
- ECCN 3A001.A.7.B
- CCATS G171972
- US HTS 8542390001
PCN/MDDS Information
SRJH0
- 99A1HF PCN
SRJLY
- 99A1NV PCN
SRJLZ
- 99A1NX PCN
SRJLQ
- 99A1NJ PCN
SRJM2
- 99A1P1 PCN
SRJPU
- 99A1VN PCN
SRJQ6
- 99A1W4 PCN
SRJLR
- 99A1NK PCN
SRJM3
- 99A1P2 PCN
SRJPV
- 99A1VP PCN
SRJQ7
- 99A1W5 PCN
SRJLS
- 99A1NL PCN
SRJM4
- 99A1P3 PCN
SRJPW
- 99A1VR PCN
SRJLT
- 99A1NM PCN
SRJPX
- 99A1VT PCN
SRJQ9
- 99A1W6 PCN
SRJLU
- 99A1NN PCN
SRJPY
- 99A1VW PCN
SRJLV
- 99A1NP PCN
SRJPZ
- 99A1VX PCN
SRJLW
- 99A1NR PCN
SRJLX
- 99A1NT PCN
SRJQ0
- 99A1VZ PCN
SRJPP
- 99A1VH PCN
SRJQ1
- 99A1W0 PCN
SRJPQ
- 99A1VJ PCN
SRJQ2
- 99A1W1 PCN
SRJLN
- 99A1NF PCN
SRJPR
- 99A1VK PCN
SRJQ3
- 99A1W2 PCN
SRJM0
- 99A1NZ PCN
SRJPS
- 99A1VL PCN
SRJLP
- 99A1NH PCN
SRJM1
- 99A1P0 PCN
SRJPT
- 99A1VM PCN
SRJQ5
- 99A1W3 PCN
Drivers and Software
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Technical Documentation
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
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Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.