Stratix® V 5SGXBB FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C3G

  • MM# 99A1HF
  • Spec Code SRJH0
  • Ordering Code 5SGXMBBR3H43C3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR1H43C2G

  • MM# 99A1NF
  • Spec Code SRJLN
  • Ordering Code 5SGXEBBR1H43C2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR1H43C2LG

  • MM# 99A1NH
  • Spec Code SRJLP
  • Ordering Code 5SGXEBBR1H43C2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR1H43I2G

  • MM# 99A1NJ
  • Spec Code SRJLQ
  • Ordering Code 5SGXEBBR1H43I2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR2H43C2G

  • MM# 99A1NK
  • Spec Code SRJLR
  • Ordering Code 5SGXEBBR2H43C2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR2H43C2LG

  • MM# 99A1NL
  • Spec Code SRJLS
  • Ordering Code 5SGXEBBR2H43C2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR2H43C3G

  • MM# 99A1NM
  • Spec Code SRJLT
  • Ordering Code 5SGXEBBR2H43C3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I2G

  • MM# 99A1NN
  • Spec Code SRJLU
  • Ordering Code 5SGXEBBR2H43I2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I2LG

  • MM# 99A1NP
  • Spec Code SRJLV
  • Ordering Code 5SGXEBBR2H43I2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I3G

  • MM# 99A1NR
  • Spec Code SRJLW
  • Ordering Code 5SGXEBBR2H43I3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR2H43I3LG

  • MM# 99A1NT
  • Spec Code SRJLX
  • Ordering Code 5SGXEBBR2H43I3LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C2G

  • MM# 99A1NV
  • Spec Code SRJLY
  • Ordering Code 5SGXEBBR3H43C2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C2LG

  • MM# 99A1NX
  • Spec Code SRJLZ
  • Ordering Code 5SGXEBBR3H43C2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C3G

  • MM# 99A1NZ
  • Spec Code SRJM0
  • Ordering Code 5SGXEBBR3H43C3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR3H43C4G

  • MM# 99A1P0
  • Spec Code SRJM1
  • Ordering Code 5SGXEBBR3H43C4G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR3H43I3G

  • MM# 99A1P1
  • Spec Code SRJM2
  • Ordering Code 5SGXEBBR3H43I3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR3H43I3LG

  • MM# 99A1P2
  • Spec Code SRJM3
  • Ordering Code 5SGXEBBR3H43I3LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXEBBR3H43I4G

  • MM# 99A1P3
  • Spec Code SRJM4
  • Ordering Code 5SGXEBBR3H43I4G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR1H43C2G

  • MM# 99A1VH
  • Spec Code SRJPP
  • Ordering Code 5SGXMBBR1H43C2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR1H43C2LG

  • MM# 99A1VJ
  • Spec Code SRJPQ
  • Ordering Code 5SGXMBBR1H43C2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR1H43I2G

  • MM# 99A1VK
  • Spec Code SRJPR
  • Ordering Code 5SGXMBBR1H43I2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I2G

  • MM# 99A1VL
  • Spec Code SRJPS
  • Ordering Code 5SGXMBBR2H40I2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I2LG

  • MM# 99A1VM
  • Spec Code SRJPT
  • Ordering Code 5SGXMBBR2H40I2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H40I3G

  • MM# 99A1VN
  • Spec Code SRJPU
  • Ordering Code 5SGXMBBR2H40I3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H43C2G

  • MM# 99A1VP
  • Spec Code SRJPV
  • Ordering Code 5SGXMBBR2H43C2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H43C2LG

  • MM# 99A1VR
  • Spec Code SRJPW
  • Ordering Code 5SGXMBBR2H43C2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H43C3G

  • MM# 99A1VT
  • Spec Code SRJPX
  • Ordering Code 5SGXMBBR2H43C3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I2G

  • MM# 99A1VW
  • Spec Code SRJPY
  • Ordering Code 5SGXMBBR2H43I2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I2LG

  • MM# 99A1VX
  • Spec Code SRJPZ
  • Ordering Code 5SGXMBBR2H43I2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I3G

  • MM# 99A1VZ
  • Spec Code SRJQ0
  • Ordering Code 5SGXMBBR2H43I3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR2H43I3LG

  • MM# 99A1W0
  • Spec Code SRJQ1
  • Ordering Code 5SGXMBBR2H43I3LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C2G

  • MM# 99A1W1
  • Spec Code SRJQ2
  • Ordering Code 5SGXMBBR3H43C2G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C2LG

  • MM# 99A1W2
  • Spec Code SRJQ3
  • Ordering Code 5SGXMBBR3H43C2LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR3H43C4G

  • MM# 99A1W3
  • Spec Code SRJQ5
  • Ordering Code 5SGXMBBR3H43C4G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR3H43I3G

  • MM# 99A1W4
  • Spec Code SRJQ6
  • Ordering Code 5SGXMBBR3H43I3G
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR3H43I3LG

  • MM# 99A1W5
  • Spec Code SRJQ7
  • Ordering Code 5SGXMBBR3H43I3LG
  • Stepping A1

Stratix® V 5SGXBB FPGA 5SGXMBBR3H43I4G

  • MM# 99A1W6
  • Spec Code SRJQ9
  • Ordering Code 5SGXMBBR3H43I4G
  • Stepping A1

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SRJH0

SRJLY

SRJLZ

SRJLQ

SRJM2

SRJPU

SRJQ6

SRJLR

SRJM3

SRJPV

SRJQ7

SRJLS

SRJM4

SRJPW

SRJLT

SRJPX

SRJQ9

SRJLU

SRJPY

SRJLV

SRJPZ

SRJLW

SRJLX

SRJQ0

SRJPP

SRJQ1

SRJPQ

SRJQ2

SRJLN

SRJPR

SRJQ3

SRJM0

SRJPS

SRJLP

SRJM1

SRJPT

SRJQ5

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.