Stratix® V 5SGSD3 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGSD3 FPGA 5SGSMD3E1H29I2G

  • MM# 999XH4
  • Spec Code SRHE1
  • Ordering Code 5SGSMD3E1H29I2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E2H29C3G

  • MM# 999XH5
  • Spec Code SRHE2
  • Ordering Code 5SGSMD3E2H29C3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E2H29I3G

  • MM# 999XH6
  • Spec Code SRHE3
  • Ordering Code 5SGSMD3E2H29I3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E2H29C2G

  • MM# 999XHL
  • Spec Code SRHEE
  • Ordering Code 5SGSMD3E2H29C2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E2H29I2G

  • MM# 999XHN
  • Spec Code SRHEF
  • Ordering Code 5SGSMD3E2H29I2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E3H29C2G

  • MM# 999XHR
  • Spec Code SRHEG
  • Ordering Code 5SGSMD3E3H29C2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H1F35C2LG

  • MM# 999XHT
  • Spec Code SRHEH
  • Ordering Code 5SGSMD3H1F35C2LG
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H3F35I3G

  • MM# 999XHV
  • Spec Code SRHEJ
  • Ordering Code 5SGSMD3H3F35I3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H3F35I3LG

  • MM# 999XHW
  • Spec Code SRHEK
  • Ordering Code 5SGSMD3H3F35I3LG
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H3F35I4G

  • MM# 999XHX
  • Spec Code SRHEL
  • Ordering Code 5SGSMD3H3F35I4G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E3H29I3G

  • MM# 999XJD
  • Spec Code SRHEY
  • Ordering Code 5SGSMD3E3H29I3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H1F35C1G

  • MM# 999XJF
  • Spec Code SRHEZ
  • Ordering Code 5SGSMD3H1F35C1G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H1F35C2G

  • MM# 999XJG
  • Spec Code SRHF0
  • Ordering Code 5SGSMD3H1F35C2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35C1G

  • MM# 999XJH
  • Spec Code SRHF1
  • Ordering Code 5SGSMD3H2F35C1G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35I3G

  • MM# 999XJJ
  • Spec Code SRHF2
  • Ordering Code 5SGSMD3H2F35I3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E1H29C1G

  • MM# 999XJR
  • Spec Code SRHF7
  • Ordering Code 5SGSMD3E1H29C1G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E3H29C3G

  • MM# 999XJX
  • Spec Code SRHFB
  • Ordering Code 5SGSMD3E3H29C3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E3H29I4G

  • MM# 999XK0
  • Spec Code SRHFD
  • Ordering Code 5SGSMD3E3H29I4G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E1H29C2G

  • MM# 999XK1
  • Spec Code SRHFE
  • Ordering Code 5SGSMD3E1H29C2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E2H29C1G

  • MM# 999XK3
  • Spec Code SRHFF
  • Ordering Code 5SGSMD3E2H29C1G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3E3H29C4G

  • MM# 999XK5
  • Spec Code SRHFH
  • Ordering Code 5SGSMD3E3H29C4G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35C2LG

  • MM# 999XK6
  • Spec Code SRHFJ
  • Ordering Code 5SGSMD3H2F35C2LG
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35C3G

  • MM# 999XKK
  • Spec Code SRHFU
  • Ordering Code 5SGSMD3H2F35C3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35I2G

  • MM# 999XKL
  • Spec Code SRHFV
  • Ordering Code 5SGSMD3H2F35I2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35I3LG

  • MM# 999XKM
  • Spec Code SRHFW
  • Ordering Code 5SGSMD3H2F35I3LG
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H3F35C2G

  • MM# 999XKN
  • Spec Code SRHFX
  • Ordering Code 5SGSMD3H3F35C2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H1F35I2G

  • MM# 999XKZ
  • Spec Code SRHG3
  • Ordering Code 5SGSMD3H1F35I2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35C2G

  • MM# 999XL0
  • Spec Code SRHG4
  • Ordering Code 5SGSMD3H2F35C2G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H2F35I2LG

  • MM# 999XL1
  • Spec Code SRHG5
  • Ordering Code 5SGSMD3H2F35I2LG
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H3F35C2LG

  • MM# 999XL2
  • Spec Code SRHG6
  • Ordering Code 5SGSMD3H3F35C2LG
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H3F35C3G

  • MM# 999XL3
  • Spec Code SRHG7
  • Ordering Code 5SGSMD3H3F35C3G
  • Stepping A1

Stratix® V 5SGSD3 FPGA 5SGSMD3H3F35C4G

  • MM# 999XL4
  • Spec Code SRHG8
  • Ordering Code 5SGSMD3H3F35C4G
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SRHF2

SRHF1

SRHF0

SRHEL

SRHEZ

SRHEY

SRHF7

SRHEK

SRHEJ

SRHEH

SRHEG

SRHEF

SRHEE

SRHE3

SRHG5

SRHE2

SRHG4

SRHE1

SRHG3

SRHFX

SRHFW

SRHG8

SRHFV

SRHG7

SRHFU

SRHG6

SRHFD

SRHFB

SRHFJ

SRHFH

SRHFF

SRHFE

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.