Stratix® V 5SGSD8 FPGA

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Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGSD8 FPGA 5SGSMD8N2F45I2G

  • MM# 99A2TP
  • SPECCode SRJSN
  • OrderingCode 5SGSMD8N2F45I2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N2F45C3G

  • MM# 99A2X2
  • SPECCode SRJUC
  • OrderingCode 5SGSED8N2F45C3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N3F45C2G

  • MM# 99A2ZN
  • SPECCode SRJVM
  • OrderingCode 5SGSMD8N3F45C2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8K3F40I3LP

  • MM# 99A6ZZ
  • SPECCode SRK70
  • OrderingCode 5SGSMD8K3F40I3LP
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N3F45I4G

  • MM# 99A2ZD
  • SPECCode SRJVE
  • OrderingCode 5SGSED8N3F45I4G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N2F45I3G

  • MM# 99A2RP
  • SPECCode SRJRU
  • OrderingCode 5SGSMD8N2F45I3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N2F46C2LG

  • MM# 99A2WC
  • SPECCode SRJTV
  • OrderingCode 5SGSED8N2F46C2LG
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N3F45C2G

  • MM# 99A2V9
  • SPECCode SRJT3
  • OrderingCode 5SGSED8N3F45C2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N2F45C2G

  • MM# 99A2VN
  • SPECCode SRJTD
  • OrderingCode 5SGSED8N2F45C2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N1F45C2G

  • MM# 99A2WZ
  • SPECCode SRJUA
  • OrderingCode 5SGSED8N1F45C2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N3F45C3G

  • MM# 99A2V2
  • SPECCode SRJSW
  • OrderingCode 5SGSED8N3F45C3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N2F45C3G

  • MM# 99A2ZT
  • SPECCode SRJVQ
  • OrderingCode 5SGSMD8N2F45C3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N1F46I2G

  • MM# 99A2TV
  • SPECCode SRJSR
  • OrderingCode 5SGSED8N1F46I2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N3F45I4G

  • MM# 99A2TZ
  • SPECCode SRJSU
  • OrderingCode 5SGSMD8N3F45I4G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N3F45I3G

  • MM# 99A2VJ
  • SPECCode SRJT9
  • OrderingCode 5SGSED8N3F45I3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N2F45C2G

  • MM# 99A2RN
  • SPECCode SRJRT
  • OrderingCode 5SGSMD8N2F45C2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N2F45I2G

  • MM# 99A301
  • SPECCode SRJVV
  • OrderingCode 5SGSED8N2F45I2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N3F45I3G

  • MM# 99A2XV
  • SPECCode SRJUY
  • OrderingCode 5SGSMD8N3F45I3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N3F45C4G

  • MM# 99A2ZW
  • SPECCode SRJVS
  • OrderingCode 5SGSED8N3F45C4G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N3F45C3G

  • MM# 99A2WA
  • SPECCode SRJTU
  • OrderingCode 5SGSMD8N3F45C3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N3F45C4G

  • MM# 99A2TH
  • SPECCode SRJSG
  • OrderingCode 5SGSMD8N3F45C4G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N1F45I2G

  • MM# 99A2XD
  • SPECCode SRJUM
  • OrderingCode 5SGSMD8N1F45I2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N3F46I3G

  • MM# 99A2WF
  • SPECCode SRJTX
  • OrderingCode 5SGSED8N3F46I3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSMD8N1F45C2G

  • MM# 99A2X4
  • SPECCode SRJUE
  • OrderingCode 5SGSMD8N1F45C2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N2F46C3G

  • MM# 99A2W8
  • SPECCode SRJTS
  • OrderingCode 5SGSED8N2F46C3G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N1F45I2G

  • MM# 99A2ZF
  • SPECCode SRJVF
  • OrderingCode 5SGSED8N1F45I2G
  • Stepping A1

Stratix® V 5SGSD8 FPGA 5SGSED8N2F45I3G

  • MM# 99A2Z3
  • SPECCode SRJV6
  • OrderingCode 5SGSED8N2F45I3G
  • Stepping A1

Trade compliance information

  • ECC Varies By Product
  • PCode Varies By Product
  • HTS Varies By Product

PCN/MDDS Information

SRJVE

SRJTD

SRJVF

SRJT9

SRJT3

SRJSR

SRJV6

SRJSU

SRJSW

SRJUY

SRJUM

SRK70

SRJSN

SRJUC

SRJUE

SRJSG

SRJUA

SRJVS

SRJTS

SRJVV

SRJTU

SRJTV

SRJRT

SRJRU

SRJTX

SRJVM

SRJVQ

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.