Stratix® V 5SGSD6 FPGA
Specifications
Compare Intel® Products
Essentials
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Product Collection
Stratix® V GS FPGA
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Marketing Status
Launched
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Launch Date
2010
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Lithography
28 nm
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Resources
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Logic Elements (LE)
583000
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Adaptive Logic Modules (ALM)
220000
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Adaptive Logic Module (ALM) Registers
880000
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Fabric and I/O Phase-Locked Loops (PLLs)
28
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Maximum Embedded Memory
51.71 Mb
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Digital Signal Processing (DSP) Blocks
1775
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP)
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Hard Memory Controllers
No
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External Memory Interfaces (EMIF)
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3
I/O Specifications
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Maximum User I/O Count†
840
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS
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Maximum LVDS Pairs
420
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Maximum Non-Return to Zero (NRZ) Transceivers†
48
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Maximum Non-Return to Zero (NRZ) Data Rate†
14.1 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Package Specifications
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Package Options
F1517, F1932
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Retired and discontinued
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SRJVG
- 99A2ZG PCN
SRJVH
- 99A2ZH PCN
SRJVJ
- 99A2ZK PCN
SR81T
- 969611 PCN
SR81S
- 969610 PCN
SRJVB
- 99A2Z9 PCN
SRJUR
- 99A2XJ PCN
SRJV5
- 99A2Z2 PCN
SRJUV
- 99A2XN PCN
SRJUW
- 99A2XP PCN
SRJV8
- 99A2Z5 PCN
SRJV9
- 99A2Z7 PCN
SRJUJ
- 99A2X8 PCN
SRJUL
- 99A2XA PCN
SRJUN
- 99A2XF PCN
SRJV1
- 99A2XX PCN
SRJV2
- 99A2XZ PCN
SRJUB
- 99A2X1 PCN
SRJUD
- 99A2X3 PCN
SRJUF
- 99A2X5 PCN
SRJUH
- 99A2X7 PCN
SRJTY
- 99A2WG PCN
SR7P6
- 969147 PCN
SR7P5
- 969146 PCN
SRJU2
- 99A2WM PCN
SRJTR
- 99A2W7 PCN
SRJU4
- 99A2WP PCN
SRJU5
- 99A2WR PCN
SRJU6
- 99A2WT PCN
SRJU7
- 99A2WV PCN
SRJU9
- 99A2WX PCN
SRJTL
- 99A2W0 PCN
SRJTN
- 99A2W3 PCN
SRJU0
- 99A2WJ PCN
SR8XV
- 970716 PCN
SRJTA
- 99A2VK PCN
SR8XU
- 970715 PCN
SR8XT
- 970714 PCN
SRJTC
- 99A2VM PCN
SR883
- 969825 PCN
SR882
- 969824 PCN
SRJTE
- 99A2VP PCN
SRJTG
- 99A2VV PCN
SRJTH
- 99A2VW PCN
SRJSZ
- 99A2V5 PCN
SR8XW
- 970717 PCN
SRJT1
- 99A2V7 PCN
SRJSQ
- 99A2TT PCN
SRJT2
- 99A2V8 PCN
SRJSS
- 99A2TW PCN
SRJT4
- 99A2VA PCN
SRJST
- 99A2TX PCN
SRJT6
- 99A2VF PCN
SRJSV
- 99A2V0 PCN
SRJT8
- 99A2VH PCN
SRJSH
- 99A2TJ PCN
SRJSJ
- 99A2TK PCN
SRJSK
- 99A2TL PCN
SRJSM
- 99A2TN PCN
SRJSC
- 99A2TC PCN
SRJSD
- 99A2TD PCN
SRJSE
- 99A2TF PCN
SRJSF
- 99A2TG PCN
SRJRX
- 99A2RV PCN
SRJS9
- 99A2T8 PCN
SRJRY
- 99A2RW PCN
SRJRZ
- 99A2RX PCN
SR86D
- 969767 PCN
SR8WD
- 970666 PCN
SR86B
- 969765 PCN
SRJS2
- 99A2T1 PCN
SRJVU
- 99A300 PCN
SRJVW
- 99A302 PCN
SRJS6
- 99A2T5 PCN
SRJRV
- 99A2RR PCN
SRJS7
- 99A2T6 PCN
SRJVK
- 99A2ZL PCN
SRJVL
- 99A2ZM PCN
SRJVN
- 99A2ZP PCN
SRJVP
- 99A2ZR PCN
SRJVR
- 99A2ZV PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.