Stratix® V 5SGSD6 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGSD6 FPGA 5SGSED6N3F45I4G

  • MM# 99A2RV
  • Spec Code SRJRX
  • Ordering Code 5SGSED6N3F45I4G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N3F45C3G

  • MM# 99A2RW
  • Spec Code SRJRY
  • Ordering Code 5SGSED6N3F45C3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N2F45C2G

  • MM# 99A2T1
  • Spec Code SRJS2
  • Ordering Code 5SGSMD6N2F45C2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N1F45I2G

  • MM# 99A2TK
  • Spec Code SRJSJ
  • Ordering Code 5SGSED6N1F45I2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N3F45C3G

  • MM# 99A2V7
  • Spec Code SRJT1
  • Ordering Code 5SGSMD6N3F45C3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N2F45C2G

  • MM# 99A2V8
  • Spec Code SRJT2
  • Ordering Code 5SGSED6N2F45C2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N1F45C2G

  • MM# 99A2VA
  • Spec Code SRJT4
  • Ordering Code 5SGSED6N1F45C2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N2F45C3G

  • MM# 99A2VF
  • Spec Code SRJT6
  • Ordering Code 5SGSMD6N2F45C3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N2F45I2G

  • MM# 99A2VW
  • Spec Code SRJTH
  • Ordering Code 5SGSED6N2F45I2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N3F45C4G

  • MM# 99A2W7
  • Spec Code SRJTR
  • Ordering Code 5SGSED6N3F45C4G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N3F45C2G

  • MM# 99A2WG
  • Spec Code SRJTY
  • Ordering Code 5SGSED6N3F45C2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N3F45I3G

  • MM# 99A2WP
  • Spec Code SRJU4
  • Ordering Code 5SGSMD6N3F45I3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N2F45I3G

  • MM# 99A2WR
  • Spec Code SRJU5
  • Ordering Code 5SGSED6N2F45I3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N2F45I3G

  • MM# 99A2X5
  • Spec Code SRJUF
  • Ordering Code 5SGSMD6N2F45I3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N3F45C2G

  • MM# 99A2X7
  • Spec Code SRJUH
  • Ordering Code 5SGSMD6N3F45C2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N3F45I4G

  • MM# 99A2XA
  • Spec Code SRJUL
  • Ordering Code 5SGSMD6N3F45I4G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N2F45C3G

  • MM# 99A2XP
  • Spec Code SRJUW
  • Ordering Code 5SGSED6N2F45C3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N1F45I2G

  • MM# 99A2XZ
  • Spec Code SRJV2
  • Ordering Code 5SGSMD6N1F45I2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSED6N3F45I3G

  • MM# 99A2Z7
  • Spec Code SRJV9
  • Ordering Code 5SGSED6N3F45I3G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N2F45I2G

  • MM# 99A2ZH
  • Spec Code SRJVH
  • Ordering Code 5SGSMD6N2F45I2G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N3F45C4G

  • MM# 99A2ZR
  • Spec Code SRJVP
  • Ordering Code 5SGSMD6N3F45C4G
  • Stepping A1

Stratix® V 5SGSD6 FPGA 5SGSMD6N1F45C2G

  • MM# 99A2ZV
  • Spec Code SRJVR
  • Ordering Code 5SGSMD6N1F45C2G
  • Stepping A1

Trade compliance information

  • ECCN 3A001.A.7.A
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SRJUF

SRJVH

SRJUH

SRJTH

SRJTY

SRJRX

SRJRY

SRJT1

SRJT2

SRJTR

SRJS2

SRJU4

SRJT4

SRJU5

SRJT6

SRJUW

SRJV9

SRJSJ

SRJUL

SRJVP

SRJV2

SRJVR

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.