Stratix® V 5SGSD5 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGSD5 FPGA 5SGSMD5H1F35C2G

  • MM# 999XLC
  • Spec Code SRHGE
  • Ordering Code 5SGSMD5H1F35C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H2F35C3G

  • MM# 999XLD
  • Spec Code SRHGF
  • Ordering Code 5SGSMD5H2F35C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H2F35I3G

  • MM# 999XLF
  • Spec Code SRHGG
  • Ordering Code 5SGSMD5H2F35I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H3F35C4G

  • MM# 999XLG
  • Spec Code SRHGH
  • Ordering Code 5SGSMD5H3F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K1F40C1G

  • MM# 999XLH
  • Spec Code SRHGJ
  • Ordering Code 5SGSMD5K1F40C1G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD5 FPGA 5SGSMD5K1F40C2G

  • MM# 999XLJ
  • Spec Code SRHGK
  • Ordering Code 5SGSMD5K1F40C2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40C1G

  • MM# 999XLK
  • Spec Code SRHGL
  • Ordering Code 5SGSMD5K2F40C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H2F35C1G

  • MM# 999XLZ
  • Spec Code SRHGV
  • Ordering Code 5SGSMD5H2F35C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40I2G

  • MM# 999XMD
  • Spec Code SRHH5
  • Ordering Code 5SGSMD5K2F40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K3F40I4G

  • MM# 999XMG
  • Spec Code SRHH6
  • Ordering Code 5SGSMD5K3F40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H1F35I2G

  • MM# 999XMM
  • Spec Code SRHHB
  • Ordering Code 5SGSMD5H1F35I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H2F35C2G

  • MM# 999XMN
  • Spec Code SRHHC
  • Ordering Code 5SGSMD5H2F35C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H3F35I4G

  • MM# 999XMT
  • Spec Code SRHHF
  • Ordering Code 5SGSMD5H3F35I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K1F40C2LG

  • MM# 999XN6
  • Spec Code SRHHR
  • Ordering Code 5SGSMD5K1F40C2LG
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40C2G

  • MM# 999XN8
  • Spec Code SRHHS
  • Ordering Code 5SGSMD5K2F40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40C2LG

  • MM# 999XN9
  • Spec Code SRHHT
  • Ordering Code 5SGSMD5K2F40C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H2F35I2G

  • MM# 999XNZ
  • Spec Code SRHJA
  • Ordering Code 5SGSMD5H2F35I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H3F35C3G

  • MM# 999XP2
  • Spec Code SRHJC
  • Ordering Code 5SGSMD5H3F35C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K1F40I2G

  • MM# 999XP3
  • Spec Code SRHJD
  • Ordering Code 5SGSMD5K1F40I2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40C3G

  • MM# 999XP4
  • Spec Code SRHJE
  • Ordering Code 5SGSMD5K2F40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K3F40C2G

  • MM# 999XPH
  • Spec Code SRHJQ
  • Ordering Code 5SGSMD5K3F40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K3F40C3G

  • MM# 999XT3
  • Spec Code SRHKX
  • Ordering Code 5SGSMD5K3F40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K3F40C4G

  • MM# 999XT4
  • Spec Code SRHKY
  • Ordering Code 5SGSMD5K3F40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K3F40I3G

  • MM# 999XT5
  • Spec Code SRHKZ
  • Ordering Code 5SGSMD5K3F40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K3F40I3LG

  • MM# 999XT6
  • Spec Code SRHL0
  • Ordering Code 5SGSMD5K3F40I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40I2LG

  • MM# 999Z18
  • Spec Code SRHQD
  • Ordering Code 5SGSMD5K2F40I2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40I3G

  • MM# 999Z19
  • Spec Code SRHQE
  • Ordering Code 5SGSMD5K2F40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K2F40I3LG

  • MM# 999Z1A
  • Spec Code SRHQF
  • Ordering Code 5SGSMD5K2F40I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5K3F40C2LG

  • MM# 999Z1C
  • Spec Code SRHQG
  • Ordering Code 5SGSMD5K3F40C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H1F35C1G

  • MM# 999Z1H
  • Spec Code SRHQL
  • Ordering Code 5SGSMD5H1F35C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H3F35C2G

  • MM# 999Z1M
  • Spec Code SRHQP
  • Ordering Code 5SGSMD5H3F35C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD5 FPGA 5SGSMD5H3F35I3G

  • MM# 999Z1N
  • Spec Code SRHQQ
  • Ordering Code 5SGSMD5H3F35I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN/MDDS Information

SRHH6

SRHKY

SRHH5

SRHKX

SRHGV

SRHKZ

SRHGE

SRHQL

SRHGL

SRHGK

SRHL0

SRHGJ

SRHGH

SRHGG

SRHQQ

SRHGF

SRHQP

SRHHT

SRHHS

SRHHR

SRHJQ

SRHQG

SRHQF

SRHQE

SRHQD

SRHHF

SRHHC

SRHJE

SRHHB

SRHJD

SRHJC

SRHJA

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.