Stratix® V 5SGSD4 FPGA

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Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGSD4 FPGA 5SGSMD4K3F40C2G

  • MM# 999XL9
  • Spec Code SRHGC
  • Ordering Code 5SGSMD4K3F40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E1H29I2G

  • MM# 999XJ1
  • Spec Code SRHEN
  • Ordering Code 5SGSMD4E1H29I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35C2G

  • MM# 999XJ7
  • Spec Code SRHEU
  • Ordering Code 5SGSMD4H2F35C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35I3G

  • MM# 999XM6
  • Spec Code SRHH1
  • Ordering Code 5SGSMD4H2F35I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K1F40I2G

  • MM# 999XJC
  • Spec Code SRHEX
  • Ordering Code 5SGSMD4K1F40I2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD4 FPGA 5SGSMD4K3F40C4G

  • MM# 999XPF
  • Spec Code SRHJN
  • Ordering Code 5SGSMD4K3F40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E1H29C2LG

  • MM# 999XKP
  • Spec Code SRHFY
  • Ordering Code 5SGSMD4E1H29C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E3H29C2G

  • MM# 999XM0
  • Spec Code SRHGW
  • Ordering Code 5SGSMD4E3H29C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40C2G

  • MM# 999XLT
  • Spec Code SRHGR
  • Ordering Code 5SGSMD4K2F40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40I3LG

  • MM# 999XLW
  • Spec Code SRHGT
  • Ordering Code 5SGSMD4K2F40I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H3F35I3G

  • MM# 999XM8
  • Spec Code SRHH2
  • Ordering Code 5SGSMD4H3F35I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29I3LG

  • MM# 999XJN
  • Spec Code SRHF5
  • Ordering Code 5SGSMD4E2H29I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E3H29C3G

  • MM# 999XJ4
  • Spec Code SRHER
  • Ordering Code 5SGSMD4E3H29C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29C2G

  • MM# 999XJ2
  • Spec Code SRHEP
  • Ordering Code 5SGSMD4E2H29C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H3F35C2G

  • MM# 999XKA
  • Spec Code SRHFN
  • Ordering Code 5SGSMD4H3F35C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35C2LG

  • MM# 999XLM
  • Spec Code SRHGM
  • Ordering Code 5SGSMD4H2F35C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35I2G

  • MM# 999XM5
  • Spec Code SRHH0
  • Ordering Code 5SGSMD4H2F35I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K3F40C2LG

  • MM# 999XMJ
  • Spec Code SRHH8
  • Ordering Code 5SGSMD4K3F40C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E3H29I3G

  • MM# 999XM3
  • Spec Code SRHGY
  • Ordering Code 5SGSMD4E3H29I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E1H29C1G

  • MM# 999XL5
  • Spec Code SRHG9
  • Ordering Code 5SGSMD4E1H29C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K3F40I3LG

  • MM# 999XML
  • Spec Code SRHHA
  • Ordering Code 5SGSMD4K3F40I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K3F40I3G

  • MM# 999XLX
  • Spec Code SRHGU
  • Ordering Code 5SGSMD4K3F40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40I2LG

  • MM# 999XKJ
  • Spec Code SRHFT
  • Ordering Code 5SGSMD4K2F40I2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H3F35C4G

  • MM# 999XLR
  • Spec Code SRHGQ
  • Ordering Code 5SGSMD4H3F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40C1G

  • MM# 999XKD
  • Spec Code SRHFQ
  • Ordering Code 5SGSMD4K2F40C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E1H29C2G

  • MM# 999XJ0
  • Spec Code SRHEM
  • Ordering Code 5SGSMD4E1H29C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29C3G

  • MM# 999XJ3
  • Spec Code SRHEQ
  • Ordering Code 5SGSMD4E2H29C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K1F40C2LG

  • MM# 999XMH
  • Spec Code SRHH7
  • Ordering Code 5SGSMD4K1F40C2LG
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD4 FPGA 5SGSMD4K1F40C2G

  • MM# 999XMC
  • Spec Code SRHH4
  • Ordering Code 5SGSMD4K1F40C2G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD4 FPGA 5SGSMD4H3F35I3LG

  • MM# 999XM9
  • Spec Code SRHH3
  • Ordering Code 5SGSMD4H3F35I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E3H29C2LG

  • MM# 999XM2
  • Spec Code SRHGX
  • Ordering Code 5SGSMD4E3H29C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29I2LG

  • MM# 999XJK
  • Spec Code SRHF3
  • Ordering Code 5SGSMD4E2H29I2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40C2LG

  • MM# 999XLV
  • Spec Code SRHGS
  • Ordering Code 5SGSMD4K2F40C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K3F40I4G

  • MM# 999XLA
  • Spec Code SRHGD
  • Ordering Code 5SGSMD4K3F40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H3F35C2LG

  • MM# 999XLP
  • Spec Code SRHGP
  • Ordering Code 5SGSMD4H3F35C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35I2LG

  • MM# 999XLN
  • Spec Code SRHGN
  • Ordering Code 5SGSMD4H2F35I2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40C3G

  • MM# 999XKF
  • Spec Code SRHFR
  • Ordering Code 5SGSMD4K2F40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35C3G

  • MM# 999XK8
  • Spec Code SRHFL
  • Ordering Code 5SGSMD4H2F35C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H1F35C1G

  • MM# 999XM4
  • Spec Code SRHGZ
  • Ordering Code 5SGSMD4H1F35C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H3F35I4G

  • MM# 999XJA
  • Spec Code SRHEW
  • Ordering Code 5SGSMD4H3F35I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29C2LG

  • MM# 999XKR
  • Spec Code SRHFZ
  • Ordering Code 5SGSMD4E2H29C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H1F35C2G

  • MM# 999XKW
  • Spec Code SRHG1
  • Ordering Code 5SGSMD4H1F35C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E3H29I3LG

  • MM# 999XJP
  • Spec Code SRHF6
  • Ordering Code 5SGSMD4E3H29I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H1F35I2G

  • MM# 999XK7
  • Spec Code SRHFK
  • Ordering Code 5SGSMD4H1F35I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40I3G

  • MM# 999XPC
  • Spec Code SRHJM
  • Ordering Code 5SGSMD4K2F40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K3F40C3G

  • MM# 999XMK
  • Spec Code SRHH9
  • Ordering Code 5SGSMD4K3F40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29I2G

  • MM# 999XL8
  • Spec Code SRHGB
  • Ordering Code 5SGSMD4E2H29I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K2F40I2G

  • MM# 999XKH
  • Spec Code SRHFS
  • Ordering Code 5SGSMD4K2F40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H3F35C3G

  • MM# 999XJ9
  • Spec Code SRHEV
  • Ordering Code 5SGSMD4H3F35C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E3H29I4G

  • MM# 999XKT
  • Spec Code SRHG0
  • Ordering Code 5SGSMD4E3H29I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4K1F40C1G

  • MM# 999XKC
  • Spec Code SRHFP
  • Ordering Code 5SGSMD4K1F40C1G
  • Stepping A1
  • ECCN 3A001.A.7.B
  • CCATS G171972

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35C1G

  • MM# 999XJ6
  • Spec Code SRHET
  • Ordering Code 5SGSMD4H2F35C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H2F35I3LG

  • MM# 999XK9
  • Spec Code SRHFM
  • Ordering Code 5SGSMD4H2F35I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29C1G

  • MM# 999XL6
  • Spec Code SRHGA
  • Ordering Code 5SGSMD4E2H29C1G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4H1F35C2LG

  • MM# 999XKX
  • Spec Code SRHG2
  • Ordering Code 5SGSMD4H1F35C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E2H29I3G

  • MM# 999XJL
  • Spec Code SRHF4
  • Ordering Code 5SGSMD4E2H29I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SGSD4 FPGA 5SGSMD4E3H29C4G

  • MM# 999XJ5
  • Spec Code SRHES
  • Ordering Code 5SGSMD4E3H29C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN/MDDS Information

SRHF4

SRHES

SRHER

SRHF3

SRHEQ

SRHEP

SRHEN

SRHEM

SRHEX

SRHEW

SRHEV

SRHEU

SRHF6

SRHF5

SRHET

SRHHA

SRHGU

SRHGT

SRHH4

SRHGS

SRHGR

SRHH3

SRHH2

SRHGQ

SRHH1

SRHGP

SRHH0

SRHGN

SRHGZ

SRHGY

SRHGX

SRHH9

SRHGW

SRHH8

SRHH7

SRHGD

SRHGC

SRHGB

SRHGA

SRHGM

SRHFT

SRHFS

SRHFR

SRHFQ

SRHG2

SRHG1

SRHFP

SRHG0

SRHFN

SRHFM

SRHFZ

SRHFY

SRHG9

SRHFL

SRHFK

SRHJN

SRHJM

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.