Stratix® V 5SEEB FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SEEB FPGA 5SEEBH40C2LG

  • MM# 99A1DK
  • Spec Code SRJGX
  • Ordering Code 5SEEBH40C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBF45C2G

  • MM# 99A1J6
  • Spec Code SRJHJ
  • Ordering Code 5SEEBF45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45C2LG

  • MM# 99A1J7
  • Spec Code SRJHK
  • Ordering Code 5SEEBF45C2LG
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45C3G

  • MM# 99A1J8
  • Spec Code SRJHL
  • Ordering Code 5SEEBF45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45C4G

  • MM# 99A1J9
  • Spec Code SRJHM
  • Ordering Code 5SEEBF45C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I2G

  • MM# 99A1JA
  • Spec Code SRJHN
  • Ordering Code 5SEEBF45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I2LG

  • MM# 99A1JC
  • Spec Code SRJHP
  • Ordering Code 5SEEBF45I2LG
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I3G

  • MM# 99A1JD
  • Spec Code SRJHQ
  • Ordering Code 5SEEBF45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I3LG

  • MM# 99A1JF
  • Spec Code SRJHR
  • Ordering Code 5SEEBF45I3LG
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I4G

  • MM# 99A1JH
  • Spec Code SRJHS
  • Ordering Code 5SEEBF45I4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBH40C2G

  • MM# 99A1JK
  • Spec Code SRJHT
  • Ordering Code 5SEEBH40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40C3G

  • MM# 99A1JL
  • Spec Code SRJHU
  • Ordering Code 5SEEBH40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40C4G

  • MM# 99A1JM
  • Spec Code SRJHV
  • Ordering Code 5SEEBH40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I2G

  • MM# 99A1JN
  • Spec Code SRJHW
  • Ordering Code 5SEEBH40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I2LG

  • MM# 99A1JP
  • Spec Code SRJHX
  • Ordering Code 5SEEBH40I2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I3G

  • MM# 99A1JR
  • Spec Code SRJHY
  • Ordering Code 5SEEBH40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I3LG

  • MM# 99A1JT
  • Spec Code SRJHZ
  • Ordering Code 5SEEBH40I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I4G

  • MM# 99A1JV
  • Spec Code SRJJ0
  • Ordering Code 5SEEBH40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Retired and discontinued

Stratix® V 5SEEB FPGA 5SEEBF45I2LN

  • MM# 965749
  • Spec Code SR4TG
  • Ordering Code 5SEEBF45I2LN
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBH40C2L

  • MM# 965750
  • Spec Code SR4TH
  • Ordering Code 5SEEBH40C2L
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I4N

  • MM# 965751
  • Spec Code SR4TJ
  • Ordering Code 5SEEBH40I4N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBF45C2N

  • MM# 966153
  • Spec Code SR559
  • Ordering Code 5SEEBF45C2N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I2N

  • MM# 966154
  • Spec Code SR55A
  • Ordering Code 5SEEBF45I2N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBH40C2LN

  • MM# 968270
  • Spec Code SR6XP
  • Ordering Code 5SEEBH40C2LN
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40C2N

  • MM# 968271
  • Spec Code SR6XQ
  • Ordering Code 5SEEBH40C2N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I3LN

  • MM# 968272
  • Spec Code SR6XR
  • Ordering Code 5SEEBH40I3LN
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBF45C2L

  • MM# 968419
  • Spec Code SR71V
  • Ordering Code 5SEEBF45C2L
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45C4N

  • MM# 969142
  • Spec Code SR7P1
  • Ordering Code 5SEEBF45C4N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I2L

  • MM# 969143
  • Spec Code SR7P2
  • Ordering Code 5SEEBF45I2L
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I3LN

  • MM# 969144
  • Spec Code SR7P3
  • Ordering Code 5SEEBF45I3LN
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBH40C3N

  • MM# 969145
  • Spec Code SR7P4
  • Ordering Code 5SEEBH40C3N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBF45C2LN

  • MM# 969760
  • Spec Code SR866
  • Ordering Code 5SEEBF45C2LN
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBF45I3NYY

  • MM# 969761
  • Spec Code SR867
  • Ordering Code 5SEEBF45I3NYY
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBH40I2LN

  • MM# 969762
  • Spec Code SR868
  • Ordering Code 5SEEBH40I2LN
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I2N

  • MM# 969763
  • Spec Code SR869
  • Ordering Code 5SEEBH40I2N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I3NYY

  • MM# 969764
  • Spec Code SR86A
  • Ordering Code 5SEEBH40I3NYY
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBF45I3N

  • MM# 970660
  • Spec Code SR8W7
  • Ordering Code 5SEEBF45I3N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBH40I2L

  • MM# 970661
  • Spec Code SR8W8
  • Ordering Code 5SEEBH40I2L
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I3L

  • MM# 970662
  • Spec Code SR8W9
  • Ordering Code 5SEEBH40I3L
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBH40I3N

  • MM# 970663
  • Spec Code SR8WA
  • Ordering Code 5SEEBH40I3N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEEB FPGA 5SEEBF45I4N

  • MM# 973803
  • Spec Code SRBNY
  • Ordering Code 5SEEBF45I4N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEEB FPGA 5SEEBH40C4N

  • MM# 973804
  • Spec Code SRBNZ
  • Ordering Code 5SEEBH40C4N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN/MDDS Information

SRJGX

SR6XR

SR6XQ

SRJJ0

SR71V

SR869

SR868

SR8W9

SR867

SR8W8

SR866

SR8W7

SR55A

SR6XP

SR4TJ

SR4TH

SR4TG

SRJHU

SRJHV

SRJHW

SRJHX

SRJHY

SRJHZ

SRJHM

SRJHN

SR7P4

SRJHP

SR7P3

SRJHQ

SR559

SR7P2

SRJHR

SR7P1

SRJHS

SRJHT

SR86A

SR8WA

SRJHJ

SRJHK

SRJHL

SRBNZ

SRBNY

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.