Stratix® V 5SEE9 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SEE9 FPGA 5SEE9F45C2G

  • MM# 99A1HK
  • Spec Code SRJH1
  • Ordering Code 5SEE9F45C2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45C2LG

  • MM# 99A1HL
  • Spec Code SRJH2
  • Ordering Code 5SEE9F45C2LG
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45C3G

  • MM# 99A1HM
  • Spec Code SRJH3
  • Ordering Code 5SEE9F45C3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45C4G

  • MM# 99A1HN
  • Spec Code SRJH4
  • Ordering Code 5SEE9F45C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I2G

  • MM# 99A1HP
  • Spec Code SRJH5
  • Ordering Code 5SEE9F45I2G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I2LG

  • MM# 99A1HR
  • Spec Code SRJH6
  • Ordering Code 5SEE9F45I2LG
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I3G

  • MM# 99A1HT
  • Spec Code SRJH7
  • Ordering Code 5SEE9F45I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I3LG

  • MM# 99A1HV
  • Spec Code SRJH8
  • Ordering Code 5SEE9F45I3LG
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I4G

  • MM# 99A1HW
  • Spec Code SRJH9
  • Ordering Code 5SEE9F45I4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9H40C2LG

  • MM# 99A1HX
  • Spec Code SRJHA
  • Ordering Code 5SEE9H40C2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40C3G

  • MM# 99A1HZ
  • Spec Code SRJHB
  • Ordering Code 5SEE9H40C3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40C4G

  • MM# 99A1J0
  • Spec Code SRJHC
  • Ordering Code 5SEE9H40C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40I2G

  • MM# 99A1J1
  • Spec Code SRJHD
  • Ordering Code 5SEE9H40I2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40I2LG

  • MM# 99A1J2
  • Spec Code SRJHE
  • Ordering Code 5SEE9H40I2LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40I3G

  • MM# 99A1J3
  • Spec Code SRJHF
  • Ordering Code 5SEE9H40I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40I3LG

  • MM# 99A1J4
  • Spec Code SRJHG
  • Ordering Code 5SEE9H40I3LG
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40I4G

  • MM# 99A1J5
  • Spec Code SRJHH
  • Ordering Code 5SEE9H40I4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40C2G

  • MM# 99A1LH
  • Spec Code SRJK8
  • Ordering Code 5SEE9H40C2G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Retired and discontinued

Stratix® V 5SEE9 FPGA 5SEE9F45C2L

  • MM# 965746
  • Spec Code SR4TD
  • Ordering Code 5SEE9F45C2L
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45C2N

  • MM# 965747
  • Spec Code SR4TE
  • Ordering Code 5SEE9F45C2N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I2LN

  • MM# 965748
  • Spec Code SR4TF
  • Ordering Code 5SEE9F45I2LN
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9H40I3N

  • MM# 966152
  • Spec Code SR558
  • Ordering Code 5SEE9H40I3N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9F45I4N

  • MM# 968268
  • Spec Code SR6XM
  • Ordering Code 5SEE9F45I4N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9H40I2LN

  • MM# 968269
  • Spec Code SR6XN
  • Ordering Code 5SEE9H40I2LN
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9F45I3N

  • MM# 968414
  • Spec Code SR71S
  • Ordering Code 5SEE9F45I3N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I2L

  • MM# 968415
  • Spec Code SR71R
  • Ordering Code 5SEE9F45I2L
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9H40C4N

  • MM# 968416
  • Spec Code SR71U
  • Ordering Code 5SEE9H40C4N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40C3N

  • MM# 969138
  • Spec Code SR7NX
  • Ordering Code 5SEE9H40C3N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40I3LN

  • MM# 969141
  • Spec Code SR7NZ
  • Ordering Code 5SEE9H40I3LN
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9F45C2LN

  • MM# 969757
  • Spec Code SR863
  • Ordering Code 5SEE9F45C2LN
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9F45I3L

  • MM# 969758
  • Spec Code SR864
  • Ordering Code 5SEE9F45I3L
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9H40I2N

  • MM# 969759
  • Spec Code SR865
  • Ordering Code 5SEE9H40I2N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9F45C4N

  • MM# 970655
  • Spec Code SR8W2
  • Ordering Code 5SEE9F45C4N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9H40C2L

  • MM# 970656
  • Spec Code SR8W3
  • Ordering Code 5SEE9H40C2L
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40C2LN

  • MM# 970657
  • Spec Code SR8W4
  • Ordering Code 5SEE9H40C2LN
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9H40I3L

  • MM# 970658
  • Spec Code SR8W5
  • Ordering Code 5SEE9H40I3L
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Stratix® V 5SEE9 FPGA 5SEE9F45C3N

  • MM# 973801
  • Spec Code SRBNW
  • Ordering Code 5SEE9F45C3N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972

Stratix® V 5SEE9 FPGA 5SEE9H40I4N

  • MM# 973802
  • Spec Code SRBNX
  • Ordering Code 5SEE9H40I4N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN/MDDS Information

SR864

SR8W5

SRJH5

SR863

SR8W4

SRJH6

SR8W3

SRJH7

SR8W2

SRJH8

SRJH9

SR71U

SRJH1

SR71S

SRJH2

SR71R

SRJH3

SR865

SRJH4

SR4TF

SR4TE

SR4TD

SR6XN

SR6XM

SRJK8

SR558

SRJHE

SRJHF

SRJHG

SR7NZ

SRJHH

SR7NX

SRBNX

SRBNW

SRJHA

SRJHB

SRJHC

SRJHD

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.