Intel® Stratix® 10 SX 400 FPGA

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I/O Specifications

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Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35I1VG

  • MM# 999LHH
  • Spec Code SRGP8
  • Ordering Code 1SX040HH3F35I1VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35I2LG

  • MM# 999LHJ
  • Spec Code SRGP9
  • Ordering Code 1SX040HH3F35I2LG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35I2VG

  • MM# 999LHK
  • Spec Code SRGPA
  • Ordering Code 1SX040HH3F35I2VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35I3VG

  • MM# 999LHL
  • Spec Code SRGPB
  • Ordering Code 1SX040HH3F35I3VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35I3XG

  • MM# 999LHM
  • Spec Code SRGPC
  • Ordering Code 1SX040HH3F35I3XG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35E1VG

  • MM# 999LP5
  • Spec Code SRGRT
  • Ordering Code 1SX040HH1F35E1VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35E2LG

  • MM# 999LP6
  • Spec Code SRGRU
  • Ordering Code 1SX040HH1F35E2LG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35E2VG

  • MM# 999LP7
  • Spec Code SRGRV
  • Ordering Code 1SX040HH1F35E2VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I1VG

  • MM# 999LP8
  • Spec Code SRGRW
  • Ordering Code 1SX040HH1F35I1VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I2LG

  • MM# 999LP9
  • Spec Code SRGRX
  • Ordering Code 1SX040HH1F35I2LG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I2VG

  • MM# 999LPA
  • Spec Code SRGRY
  • Ordering Code 1SX040HH1F35I2VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35E1VG

  • MM# 999LPC
  • Spec Code SRGRZ
  • Ordering Code 1SX040HH2F35E1VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35E2VG

  • MM# 999LPR
  • Spec Code SRGS1
  • Ordering Code 1SX040HH2F35E2VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35E2LG

  • MM# 999LPT
  • Spec Code SRGS2
  • Ordering Code 1SX040HH2F35E2LG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I1VG

  • MM# 999LPV
  • Spec Code SRGS3
  • Ordering Code 1SX040HH2F35I1VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I2LG

  • MM# 999LPW
  • Spec Code SRGS4
  • Ordering Code 1SX040HH2F35I2LG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I2VG

  • MM# 999LPX
  • Spec Code SRGS5
  • Ordering Code 1SX040HH2F35I2VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35E1VG

  • MM# 999LR0
  • Spec Code SRGS6
  • Ordering Code 1SX040HH3F35E1VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35E2LG

  • MM# 999LR1
  • Spec Code SRGS7
  • Ordering Code 1SX040HH3F35E2LG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35E2VG

  • MM# 999LRC
  • Spec Code SRGS8
  • Ordering Code 1SX040HH3F35E2VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35E3VG

  • MM# 999LRD
  • Spec Code SRGS9
  • Ordering Code 1SX040HH3F35E3VG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35E3XG

  • MM# 999LRF
  • Spec Code SRGSB
  • Ordering Code 1SX040HH3F35E3XG
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I1VGAS

  • MM# 999VGM
  • Spec Code SRH5T
  • Ordering Code 1SX040HH1F35I1VGAS
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I2VGAS

  • MM# 999VGN
  • Spec Code SRH5U
  • Ordering Code 1SX040HH1F35I2VGAS
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I1VGAS

  • MM# 999VGP
  • Spec Code SRH5V
  • Ordering Code 1SX040HH2F35I1VGAS
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I2LGAS

  • MM# 999VGR
  • Spec Code SRH5W
  • Ordering Code 1SX040HH2F35I2LGAS
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I2VGAS

  • MM# 999VGT
  • Spec Code SRH5X
  • Ordering Code 1SX040HH2F35I2VGAS
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35I3VGAS

  • MM# 999VGV
  • Spec Code SRH5Y
  • Ordering Code 1SX040HH3F35I3VGAS
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I2LGAS

  • MM# 999VH4
  • Spec Code SRH62
  • Ordering Code 1SX040HH1F35I2LGAS
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I2LGBK

  • MM# 99A73G
  • Spec Code SRK87
  • Ordering Code 1SX040HH1F35I2LGBK
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I1VGBK

  • MM# 99A73P
  • Spec Code SRK8E
  • Ordering Code 1SX040HH1F35I1VGBK
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH1F35I2VGBK

  • MM# 99A73R
  • Spec Code SRK8F
  • Ordering Code 1SX040HH1F35I2VGBK
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I1VGBK

  • MM# 99A745
  • Spec Code SRK8G
  • Ordering Code 1SX040HH2F35I1VGBK
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I2LGBK

  • MM# 99A746
  • Spec Code SRK8H
  • Ordering Code 1SX040HH2F35I2LGBK
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH2F35I2VGBK

  • MM# 99A747
  • Spec Code SRK8J
  • Ordering Code 1SX040HH2F35I2VGBK
  • Stepping A0

Intel® Stratix® 10 SX 400 FPGA 1SX040HH3F35I3VGBK

  • MM# 99A748
  • Spec Code SRK8K
  • Ordering Code 1SX040HH3F35I3VGBK
  • Stepping A0

Trade compliance information

  • ECCN 5A002U
  • CCATS G178951
  • US HTS 8542390001

PCN/MDDS Information

SRGP9

SRGP8

SRGPC

SRGPB

SRGPA

SRGSB

SRK8E

SRK8F

SRK8G

SRK8H

SRK8J

SRGRZ

SRK8K

SRGS2

SRGS1

SRH62

SRK87

SRGRY

SRGRX

SRGS9

SRGRW

SRGS8

SRH5Y

SRGRV

SRGS7

SRH5X

SRGRU

SRGS6

SRH5W

SRGRT

SRGS5

SRH5V

SRGS4

SRH5U

SRGS3

SRH5T

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.