Intel® Stratix® 10 MX 1650 FPGA
Specifications
Compare Intel® Products
Essentials
-
Product Collection
Intel® Stratix® 10 MX FPGA
-
Marketing Status
Launched
-
Launch Date
2017
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Lithography
14 nm
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Resources
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Logic Elements (LE)
1679000
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Adaptive Logic Modules (ALM)
569200
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Adaptive Logic Module (ALM) Registers
2276800
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Fabric and I/O Phase-Locked Loops (PLLs)
16
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Maximum Embedded Memory
223.5 Mb
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Maximum High Bandwidth Memory (HBM)†
16 GB
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Digital Signal Processing (DSP) Blocks
3326
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR, DDR2, DDR3, DDR4, HMC, MoSys, QDR II, QDR II+, RLDRAM II, RLDRAM 3
I/O Specifications
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Maximum User I/O Count†
656
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
312
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Maximum Non-Return to Zero (NRZ) Transceivers†
96
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Maximum Non-Return to Zero (NRZ) Data Rate†
28.9 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
36
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
57.8 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3, 10/25/100G Ethernet
Advanced Technologies
Package Specifications
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Package Options
F2597, F2912
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E3VGBK
- MM# 99A7V2
- Spec Code SRKDF
- Ordering Code 1SM16BEU3F55E3VGBK
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E2VGBK
- MM# 99A7W1
- Spec Code SRKE3
- Ordering Code 1SM16BHU2F53E2VGBK
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU1F53E2VGNE
- MM# 99AKXA
- Spec Code SRL11
- Ordering Code 1SM16BHU1F53E2VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E1VGNE
- MM# 99AKXC
- Spec Code SRL12
- Ordering Code 1SM16BHU2F53E1VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU2F53E2VGNE
- MM# 99AKXD
- Spec Code SRL13
- Ordering Code 1SM16BHU2F53E2VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E1VGNE
- MM# 99AKXF
- Spec Code SRL14
- Ordering Code 1SM16BHU3F53E1VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E2VGNE
- MM# 99AKXG
- Spec Code SRL15
- Ordering Code 1SM16BHU3F53E2VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU3F53E3VGNE
- MM# 99AKXH
- Spec Code SRL16
- Ordering Code 1SM16BHU3F53E3VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU1F55E1VGNE
- MM# 99AKXJ
- Spec Code SRL17
- Ordering Code 1SM16BEU1F55E1VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU1F55E2VGNE
- MM# 99AKXK
- Spec Code SRL18
- Ordering Code 1SM16BEU1F55E2VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU2F55E1VGNE
- MM# 99AKXL
- Spec Code SRL19
- Ordering Code 1SM16BEU2F55E1VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E1VGNE
- MM# 99AKXM
- Spec Code SRL1A
- Ordering Code 1SM16BEU3F55E1VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E3VGNE
- MM# 99AKXN
- Spec Code SRL1B
- Ordering Code 1SM16BEU3F55E3VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BHU1F53E1VGNE
- MM# 99AL0G
- Spec Code SRL24
- Ordering Code 1SM16BHU1F53E1VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU2F55E2VGNE
- MM# 99AL0H
- Spec Code SRL25
- Ordering Code 1SM16BEU2F55E2VGNE
- Stepping B0
Intel® Stratix® 10 MX 1650 FPGA 1SM16BEU3F55E2VGNE
- MM# 99AL0J
- Spec Code SRL26
- Ordering Code 1SM16BEU3F55E2VGNE
- Stepping B0
Retired and discontinued
Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU1F53E1VG
- MM# 985063
- Spec Code SRETP
- Ordering Code 1SM16CHU1F53E1VG
- Stepping B0
- MDDS Content IDs 798373, 799022, 799195, 799287, 799615, 800035, 800459, 801340, 801759, 802701, 805357, 806087, 806863, 809000, 809077, 809465, 809497, 809826, 809850, 809938, 810501
Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU1F53E2VG
- MM# 985064
- Spec Code SRETQ
- Ordering Code 1SM16CHU1F53E2VG
- Stepping B0
- MDDS Content IDs 798373, 799022, 799195, 799287, 799615, 800035, 800459, 801340, 801759, 802701, 805357, 806087, 806863, 809000, 809077, 809465, 809497, 809826, 809850, 809938, 810501
Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU2F53E1VG
- MM# 985065
- Spec Code SRETR
- Ordering Code 1SM16CHU2F53E1VG
- Stepping B0
- MDDS Content IDs 798373, 799022, 799195, 799287, 799615, 800035, 800459, 801340, 801759, 802701, 805357, 806087, 806863, 809000, 809077, 809465, 809497, 809826, 809850, 809938, 810501
Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU2F53E2VG
- MM# 985066
- Spec Code SRETS
- Ordering Code 1SM16CHU2F53E2VG
- Stepping B0
- MDDS Content IDs 798373, 799022, 799195, 799287, 799615, 800035, 800459, 801340, 801759, 802701, 805357, 806087, 806863, 809000, 809077, 809465, 809497, 809826, 809850, 809938, 810501
Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E1VG
- MM# 985067
- Spec Code SRETT
- Ordering Code 1SM16CHU3F53E1VG
- Stepping B0
- MDDS Content IDs 798373, 799022, 799195, 799287, 799615, 800035, 800459, 801340, 801759, 802701, 805357, 806087, 806863, 809000, 809077, 809465, 809497, 809826, 809850, 809938, 810501
Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E2VG
- MM# 985068
- Spec Code SRETU
- Ordering Code 1SM16CHU3F53E2VG
- Stepping B0
- MDDS Content IDs 798373, 799022, 799195, 799287, 799615, 800035, 800459, 801340, 801759, 802701, 805357, 806087, 806863, 809000, 809077, 809465, 809497, 809826, 809850, 809938, 810501
Intel® Stratix® 10 MX 1650 FPGA 1SM16CHU3F53E3VG
- MM# 985070
- Spec Code SRETV
- Ordering Code 1SM16CHU3F53E3VG
- Stepping B0
- MDDS Content IDs 798373, 799022, 799195, 799287, 799615, 800035, 800459, 801340, 801759, 802701, 805357, 806087, 806863, 809000, 809077, 809465, 809497, 809826, 809850, 809938, 810501
Trade compliance information
- ECCN 3A001.A.7.B
- CCATS G171972
- US HTS 8542390001
PCN Information
SRFXE
- 999GKA PCN
SRL1A
- 99AKXM PCN
SRL1B
- 99AKXN PCN
SRL1C
- 99AKXV PCN
SRETM
- 985059 PCN
SREZS
- 986617 PCN
SRL14
- 99AKXF PCN
SRETL
- 985058 PCN
SREZR
- 986610 PCN
SRL15
- 99AKXG PCN
SRETK
- 985057 PCN
SREZQ
- 986598 PCN
SRL16
- 99AKXH PCN
SRETJ
- 985056 PCN
SREZP
- 986587 PCN
SRL17
- 99AKXJ PCN
SRFXL
- 999GKL PCN
SRL18
- 99AKXK PCN
SRETH
- 985055 PCN
SREZN
- 986571 PCN
SRL19
- 99AKXL PCN
SRETG
- 985054 PCN
SRL11
- 99AKXA PCN
SRL12
- 99AKXC PCN
SRL13
- 99AKXD PCN
SRKE3
- 99A7W1 PCN
SRL2A
- 99AL0N PCN
SRL2B
- 99AL0P PCN
SRL25
- 99AL0H PCN
SRL26
- 99AL0J PCN
SRL29
- 99AL0M PCN
SRETU
- 985068 PCN
SRETT
- 985067 PCN
SRETS
- 985066 PCN
SRETR
- 985065 PCN
SRETQ
- 985064 PCN
SRETP
- 985063 PCN
SRKDF
- 99A7V2 PCN
SRETN
- 985062 PCN
SRL24
- 99AL0G PCN
SRL1H
- 99AKZ6 PCN
SRL1J
- 99AKZ8 PCN
SRETV
- 985070 PCN
SRF01
- 986627 PCN
SRL1K
- 99AKZ9 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Maximum High Bandwidth Memory (HBM)†
The total capacity of all the in-package high-bandwidth memory stacks in the Intel device or component.
† Actual count could be lower depending on package.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.