Intel® Stratix® 10 GX 1650 FPGA

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Ordering and spec information

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN3F43E2VG

  • MM# 981008
  • Spec Code SRD4Q
  • Ordering Code 1SG165HN3F43E2VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN2F43I2VGAS

  • MM# 999K4T
  • Spec Code SRGL6
  • Ordering Code 1SG165HN2F43I2VGAS
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43E1VG

  • MM# 986261
  • Spec Code SREWY
  • Ordering Code 1SG166HN3F43E1VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN3F43E3VG

  • MM# 981009
  • Spec Code SRD4R
  • Ordering Code 1SG165HN3F43E3VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN1F43I1VG

  • MM# 986252
  • Spec Code SREWP
  • Ordering Code 1SG166HN1F43I1VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN3F43I3VG

  • MM# 981011
  • Spec Code SRD4T
  • Ordering Code 1SG165HN3F43I3VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU3F50I2VG

  • MM# 981023
  • Spec Code SRD50
  • Ordering Code 1SG165HU3F50I2VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN2F43I2VG

  • MM# 986260
  • Spec Code SREWX
  • Ordering Code 1SG166HN2F43I2VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU2F50E2VG

  • MM# 981014
  • Spec Code SRD4W
  • Ordering Code 1SG165HU2F50E2VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN2F43E2LG

  • MM# 986256
  • Spec Code SREWT
  • Ordering Code 1SG166HN2F43E2LG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43I1VG

  • MM# 986266
  • Spec Code SREX3
  • Ordering Code 1SG166HN3F43I1VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN1F43E2VG

  • MM# 986250
  • Spec Code SREWN
  • Ordering Code 1SG166HN1F43E2VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN1F43E2VG

  • MM# 981000
  • Spec Code SRD4L
  • Ordering Code 1SG165HN1F43E2VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU1F50I2VG

  • MM# 981013
  • Spec Code SRD4V
  • Ordering Code 1SG165HU1F50I2VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN1F43I2VG

  • MM# 981001
  • Spec Code SRD4M
  • Ordering Code 1SG165HN1F43I2VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN2F43E2VG

  • MM# 986257
  • Spec Code SREWU
  • Ordering Code 1SG166HN2F43E2VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN1F43I2LG

  • MM# 986253
  • Spec Code SREWQ
  • Ordering Code 1SG166HN1F43I2LG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43I2VG

  • MM# 986268
  • Spec Code SREX5
  • Ordering Code 1SG166HN3F43I2VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN2F43I2VG

  • MM# 981003
  • Spec Code SRD4P
  • Ordering Code 1SG165HN2F43I2VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU1F50E2VG

  • MM# 981012
  • Spec Code SRD4U
  • Ordering Code 1SG165HU1F50E2VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN2F43E1VG

  • MM# 986255
  • Spec Code SREWS
  • Ordering Code 1SG166HN2F43E1VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN2F43I1VG

  • MM# 986258
  • Spec Code SREWV
  • Ordering Code 1SG166HN2F43I1VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43I3VG

  • MM# 986269
  • Spec Code SREX6
  • Ordering Code 1SG166HN3F43I3VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU3F50E2VG

  • MM# 981020
  • Spec Code SRD4Y
  • Ordering Code 1SG165HU3F50E2VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN2F43E2VG

  • MM# 981002
  • Spec Code SRD4N
  • Ordering Code 1SG165HN2F43E2VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43E2VG

  • MM# 986263
  • Spec Code SREX0
  • Ordering Code 1SG166HN3F43E2VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43I3XG

  • MM# 986270
  • Spec Code SREX7
  • Ordering Code 1SG166HN3F43I3XG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43E3XG

  • MM# 986265
  • Spec Code SREX2
  • Ordering Code 1SG166HN3F43E3XG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN1F43E1VG

  • MM# 986245
  • Spec Code SREWL
  • Ordering Code 1SG166HN1F43E1VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU3F50I3VG

  • MM# 981024
  • Spec Code SRD51
  • Ordering Code 1SG165HU3F50I3VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN1F43I2VG

  • MM# 986254
  • Spec Code SREWR
  • Ordering Code 1SG166HN1F43I2VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43E2LG

  • MM# 986262
  • Spec Code SREWZ
  • Ordering Code 1SG166HN3F43E2LG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU2F50I2VG

  • MM# 981015
  • Spec Code SRD4X
  • Ordering Code 1SG165HU2F50I2VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN3F43I2VGAS

  • MM# 999A2W
  • Spec Code SRF5E
  • Ordering Code 1SG165HN3F43I2VGAS
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HU3F50E3VG

  • MM# 981022
  • Spec Code SRD4Z
  • Ordering Code 1SG165HU3F50E3VG
  • Stepping C2
  • ECCN 3A001.A.7.A

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43E3VG

  • MM# 986264
  • Spec Code SREX1
  • Ordering Code 1SG166HN3F43E3VG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN1F43E2LG

  • MM# 986247
  • Spec Code SREWM
  • Ordering Code 1SG166HN1F43E2LG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN2F43I2LG

  • MM# 986259
  • Spec Code SREWW
  • Ordering Code 1SG166HN2F43I2LG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG166HN3F43I2LG

  • MM# 986267
  • Spec Code SREX4
  • Ordering Code 1SG166HN3F43I2LG
  • Stepping B0
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN3F43I3VGAS

  • MM# 999A2X
  • Spec Code SRF5F
  • Ordering Code 1SG165HN3F43I3VGAS
  • Stepping C2
  • ECCN 3A001.A.7.B

Intel® Stratix® 10 GX 1650 FPGA 1SG165HN3F43I2VG

  • MM# 981010
  • Spec Code SRD4S
  • Ordering Code 1SG165HN3F43I2VG
  • Stepping C2
  • ECCN 3A001.A.7.B

Trade compliance information

  • ECCN Varies By Product
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SRF5E

SRGL6

SRF5F

SREWX

SRD4V

SRD4U

SREWW

SRD4T

SREWV

SREX7

SREWU

SREX6

SRD4S

SRD4R

SREWT

SREX5

SRD4Q

SREWS

SREX4

SREX3

SRD4P

SRD51

SREWR

SRD50

SREWQ

SREX2

SRD4Z

SRD4Y

SREWZ

SRD4X

SREWY

SRD4W

SREWP

SRD4N

SREX1

SRD4M

SREX0

SREWN

SRD4L

SREWM

SREWL

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.