Intel® Stratix® 10 GX 850 FPGA

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Ordering and Compliance

Ordering and spec information

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43E1VG

  • MM# 983376
  • Spec Code SRELX
  • Ordering Code 1SG085HN1F43E1VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43E2LG

  • MM# 983377
  • Spec Code SRELY
  • Ordering Code 1SG085HN1F43E2LG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43E2VG

  • MM# 983378
  • Spec Code SRELZ
  • Ordering Code 1SG085HN1F43E2VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I1VG

  • MM# 983379
  • Spec Code SREM0
  • Ordering Code 1SG085HN1F43I1VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I2LG

  • MM# 983380
  • Spec Code SREM1
  • Ordering Code 1SG085HN1F43I2LG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I2VG

  • MM# 983381
  • Spec Code SREM2
  • Ordering Code 1SG085HN1F43I2VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43E1VG

  • MM# 983382
  • Spec Code SREM3
  • Ordering Code 1SG085HN2F43E1VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43E2LG

  • MM# 983383
  • Spec Code SREM4
  • Ordering Code 1SG085HN2F43E2LG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43E2VG

  • MM# 983384
  • Spec Code SREM5
  • Ordering Code 1SG085HN2F43E2VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43I1VG

  • MM# 983385
  • Spec Code SREM7
  • Ordering Code 1SG085HN2F43I1VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43I2LG

  • MM# 983386
  • Spec Code SREM8
  • Ordering Code 1SG085HN2F43I2LG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43I2VG

  • MM# 983387
  • Spec Code SREM9
  • Ordering Code 1SG085HN2F43I2VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E1VG

  • MM# 983388
  • Spec Code SREMA
  • Ordering Code 1SG085HN3F43E1VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E2LG

  • MM# 983389
  • Spec Code SREMB
  • Ordering Code 1SG085HN3F43E2LG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E3VG

  • MM# 983665
  • Spec Code SREMC
  • Ordering Code 1SG085HN3F43E3VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E3XG

  • MM# 983667
  • Spec Code SREMD
  • Ordering Code 1SG085HN3F43E3XG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43I1VG

  • MM# 983668
  • Spec Code SREME
  • Ordering Code 1SG085HN3F43I1VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43I2LG

  • MM# 983669
  • Spec Code SREMF
  • Ordering Code 1SG085HN3F43I2LG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43I2VG

  • MM# 983670
  • Spec Code SREMG
  • Ordering Code 1SG085HN3F43I2VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43I3VG

  • MM# 983671
  • Spec Code SREMH
  • Ordering Code 1SG085HN3F43I3VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43I3XG

  • MM# 983672
  • Spec Code SREMJ
  • Ordering Code 1SG085HN3F43I3XG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E2VG

  • MM# 983807
  • Spec Code SREPK
  • Ordering Code 1SG085HN3F43E2VG
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E2VGAS

  • MM# 986642
  • Spec Code SRF0A
  • Ordering Code 1SG085HN3F43E2VGAS
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I1VGAS

  • MM# 999GH6
  • Spec Code SRFW7
  • Ordering Code 1SG085HN1F43I1VGAS
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I2LGAS

  • MM# 999GH8
  • Spec Code SRFW8
  • Ordering Code 1SG085HN1F43I2LGAS
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I2VGAS

  • MM# 999GHA
  • Spec Code SRFW9
  • Ordering Code 1SG085HN1F43I2VGAS
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43I2VGAS

  • MM# 999GHC
  • Spec Code SRFWA
  • Ordering Code 1SG085HN2F43I2VGAS
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E3VGAS

  • MM# 999GHD
  • Spec Code SRFWB
  • Ordering Code 1SG085HN3F43E3VGAS
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I2LGBK

  • MM# 99A7MC
  • Spec Code SRKBW
  • Ordering Code 1SG085HN1F43I2LGBK
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN1F43I2VGBK

  • MM# 99A7MD
  • Spec Code SRKBX
  • Ordering Code 1SG085HN1F43I2VGBK
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN2F43I2VGBK

  • MM# 99A7MF
  • Spec Code SRKBY
  • Ordering Code 1SG085HN2F43I2VGBK
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E2VGBK

  • MM# 99A7MG
  • Spec Code SRKBZ
  • Ordering Code 1SG085HN3F43E2VGBK
  • Stepping A1

Intel® Stratix® 10 GX 850 FPGA 1SG085HN3F43E3VGBK

  • MM# 99A7MH
  • Spec Code SRKC0
  • Ordering Code 1SG085HN3F43E3VGBK
  • Stepping A1

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SREMJ

SREMH

SREMG

SRKBW

SRKBX

SRKBY

SRKBZ

SRKC0

SRELZ

SRELY

SRELX

SREM9

SRFWB

SREM8

SRFWA

SREM7

SREMF

SREME

SREMD

SREMC

SREMB

SREMA

SRF0A

SRFW7

SREPK

SREM5

SREM4

SREM3

SREM2

SREM1

SREM0

SRFW9

SRFW8

Drivers and Software

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Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.