Intel® Stratix® 10 GX 400 FPGA

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Ordering and Compliance

Ordering and spec information

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I1VG

  • MM# 999LNX
  • SPECCode SRGRL
  • OrderingCode 1SG040HH2F35I1VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35E2VG

  • MM# 999LNW
  • SPECCode SRGRK
  • OrderingCode 1SG040HH2F35E2VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I1VGBK

  • MM# 99A73K
  • SPECCode SRK8A
  • OrderingCode 1SG040HH2F35I1VGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35I3VG

  • MM# 999LJH
  • SPECCode SRGPG
  • OrderingCode 1SG040HH3F35I3VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I1VG

  • MM# 999LNN
  • SPECCode SRGRE
  • OrderingCode 1SG040HH1F35I1VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35E2LG

  • MM# 999LP1
  • SPECCode SRGRP
  • OrderingCode 1SG040HH3F35E2LG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I2VGAS

  • MM# 999VH2
  • SPECCode SRH61
  • OrderingCode 1SG040HH1F35I2VGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I1VGAS

  • MM# 999VH5
  • SPECCode SRH63
  • OrderingCode 1SG040HH1F35I1VGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35I1VG

  • MM# 999LJ5
  • SPECCode SRGPD
  • OrderingCode 1SG040HH3F35I1VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I2VG

  • MM# 999LNR
  • SPECCode SRGRG
  • OrderingCode 1SG040HH1F35I2VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35E2LG

  • MM# 999LNV
  • SPECCode SRGRJ
  • OrderingCode 1SG040HH2F35E2LG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I2VGBK

  • MM# 99A73M
  • SPECCode SRK8C
  • OrderingCode 1SG040HH2F35I2VGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35I2LG

  • MM# 999LJ6
  • SPECCode SRGPE
  • OrderingCode 1SG040HH3F35I2LG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35E1VGAS

  • MM# 999VGZ
  • SPECCode SRH60
  • OrderingCode 1SG040HH1F35E1VGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35E1VG

  • MM# 999LNT
  • SPECCode SRGRH
  • OrderingCode 1SG040HH2F35E1VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35E3XG

  • MM# 999LP4
  • SPECCode SRGRS
  • OrderingCode 1SG040HH3F35E3XG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I2LG

  • MM# 999LNP
  • SPECCode SRGRF
  • OrderingCode 1SG040HH1F35I2LG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I2LGBK

  • MM# 99A73J
  • SPECCode SRK89
  • OrderingCode 1SG040HH1F35I2LGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35E1VGBK

  • MM# 99A73D
  • SPECCode SRK85
  • OrderingCode 1SG040HH1F35E1VGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35E2VG

  • MM# 999LP2
  • SPECCode SRGRQ
  • OrderingCode 1SG040HH3F35E2VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35E2LG

  • MM# 999LNL
  • SPECCode SRGRC
  • OrderingCode 1SG040HH1F35E2LG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I1VGAS

  • MM# 999VGH
  • SPECCode SRH5P
  • OrderingCode 1SG040HH2F35I1VGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I2LGBK

  • MM# 99A73L
  • SPECCode SRK8B
  • OrderingCode 1SG040HH2F35I2LGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35E2VG

  • MM# 999LNM
  • SPECCode SRGRD
  • OrderingCode 1SG040HH1F35E2VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I2VG

  • MM# 999LHG
  • SPECCode SRGP7
  • OrderingCode 1SG040HH2F35I2VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35I3XG

  • MM# 999LJJ
  • SPECCode SRGPH
  • OrderingCode 1SG040HH3F35I3XG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35E1VG

  • MM# 999LNK
  • SPECCode SRGRB
  • OrderingCode 1SG040HH1F35E1VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35E1VG

  • MM# 999LP0
  • SPECCode SRGRN
  • OrderingCode 1SG040HH3F35E1VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I2VGAS

  • MM# 999VGK
  • SPECCode SRH5R
  • OrderingCode 1SG040HH2F35I2VGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I2LG

  • MM# 999LNZ
  • SPECCode SRGRM
  • OrderingCode 1SG040HH2F35I2LG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35I3VGBK

  • MM# 99A73N
  • SPECCode SRK8D
  • OrderingCode 1SG040HH3F35I3VGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35I2VG

  • MM# 999LJ7
  • SPECCode SRGPF
  • OrderingCode 1SG040HH3F35I2VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35E2LGBK

  • MM# 99A738
  • SPECCode SRK84
  • OrderingCode 1SG040HH2F35E2LGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I1VGBK

  • MM# 99A73H
  • SPECCode SRK88
  • OrderingCode 1SG040HH1F35I1VGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35E3VG

  • MM# 999LP3
  • SPECCode SRGRR
  • OrderingCode 1SG040HH3F35E3VG
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH3F35I3VGAS

  • MM# 999VGL
  • SPECCode SRH5S
  • OrderingCode 1SG040HH3F35I3VGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I2VGBK

  • MM# 99A73F
  • SPECCode SRK86
  • OrderingCode 1SG040HH1F35I2VGBK
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH1F35I2LGAS

  • MM# 999VGG
  • SPECCode SRH5N
  • OrderingCode 1SG040HH1F35I2LGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35E2LGAS

  • MM# 999VGW
  • SPECCode SRH5Z
  • OrderingCode 1SG040HH2F35E2LGAS
  • Stepping A0

Intel® Stratix® 10 GX 400 FPGA 1SG040HH2F35I2LGAS

  • MM# 999VGJ
  • SPECCode SRH5Q
  • OrderingCode 1SG040HH2F35I2LGAS
  • Stepping A0

Trade compliance information

  • ECC Varies By Product
  • PCode Varies By Product
  • HTS Varies By Product

PCN/MDDS Information

SRGPG

SRGRH

SRGPF

SRGRG

SRGPE

SRGPD

SRGRF

SRGRE

SRGRD

SRGRC

SRGRB

SRGP7

SRK8D

SRK8A

SRK8B

SRK8C

SRGRQ

SRK84

SRH5S

SRGRP

SRH63

SRK85

SRH5R

SRK86

SRH5Q

SRH61

SRH5P

SRGRN

SRH60

SRGRM

SRK88

SRGRL

SRK89

SRH5N

SRGRK

SRGRJ

SRGPH

SRH5Z

SRGRS

SRGRR

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.