Intel® Stratix® 10 GX 650 FPGA

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Ordering and spec information

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35I3VGAS

  • MM# 99A7KA
  • SPECCode SRKB7
  • OrderingCode 1SG065HH3F35I3VGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35E2LG

  • MM# 999LJV
  • SPECCode SRGPR
  • OrderingCode 1SG065HH2F35E2LG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35E1VG

  • MM# 999LJK
  • SPECCode SRGPJ
  • OrderingCode 1SG065HH1F35E1VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35E2LG

  • MM# 999LJL
  • SPECCode SRGPK
  • OrderingCode 1SG065HH1F35E2LG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35I1VG

  • MM# 999LK7
  • SPECCode SRGQ1
  • OrderingCode 1SG065HH3F35I1VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35I1VG

  • MM# 999LJN
  • SPECCode SRGPM
  • OrderingCode 1SG065HH1F35I1VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35E2LG

  • MM# 999LK2
  • SPECCode SRGPX
  • OrderingCode 1SG065HH3F35E2LG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35E3VG

  • MM# 999LK4
  • SPECCode SRGPZ
  • OrderingCode 1SG065HH3F35E3VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35E2VG

  • MM# 999LK3
  • SPECCode SRGPY
  • OrderingCode 1SG065HH3F35E2VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35I1VGAS

  • MM# 99A7K5
  • SPECCode SRKB2
  • OrderingCode 1SG065HH1F35I1VGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35E3XG

  • MM# 999LK5
  • SPECCode SRGQ0
  • OrderingCode 1SG065HH3F35E3XG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35I3VG

  • MM# 999LKC
  • SPECCode SRGQ4
  • OrderingCode 1SG065HH3F35I3VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35I2LG

  • MM# 999LK8
  • SPECCode SRGQ2
  • OrderingCode 1SG065HH3F35I2LG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35I2VG

  • MM# 999LJR
  • SPECCode SRGPP
  • OrderingCode 1SG065HH1F35I2VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35E2VG

  • MM# 999LJW
  • SPECCode SRGPS
  • OrderingCode 1SG065HH2F35E2VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35I3XG

  • MM# 999LKD
  • SPECCode SRGQ5
  • OrderingCode 1SG065HH3F35I3XG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35I2VG

  • MM# 999LK0
  • SPECCode SRGPV
  • OrderingCode 1SG065HH2F35I2VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35E1VG

  • MM# 999LJT
  • SPECCode SRGPQ
  • OrderingCode 1SG065HH2F35E1VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35I2VGAS

  • MM# 99A7KC
  • SPECCode SRKB8
  • OrderingCode 1SG065HH2F35I2VGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35E3VGAS

  • MM# 99A7K2
  • SPECCode SRKAZ
  • OrderingCode 1SG065HH3F35E3VGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35I1VG

  • MM# 999LJX
  • SPECCode SRGPT
  • OrderingCode 1SG065HH2F35I1VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35E2LGAS

  • MM# 99A7K1
  • SPECCode SRKAY
  • OrderingCode 1SG065HH2F35E2LGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35I1VGAS

  • MM# 99A7K8
  • SPECCode SRKB5
  • OrderingCode 1SG065HH2F35I1VGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35I2LG

  • MM# 999LJP
  • SPECCode SRGPN
  • OrderingCode 1SG065HH1F35I2LG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35I2VG

  • MM# 999LKA
  • SPECCode SRGQ3
  • OrderingCode 1SG065HH3F35I2VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35I2LGAS

  • MM# 99A7K6
  • SPECCode SRKB3
  • OrderingCode 1SG065HH1F35I2LGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35I2VGAS

  • MM# 99A7K4
  • SPECCode SRKB1
  • OrderingCode 1SG065HH1F35I2VGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35I2LGAS

  • MM# 99A7K9
  • SPECCode SRKB6
  • OrderingCode 1SG065HH2F35I2LGAS
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH3F35E1VG

  • MM# 999LK1
  • SPECCode SRGPW
  • OrderingCode 1SG065HH3F35E1VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35E2VG

  • MM# 999LJM
  • SPECCode SRGPL
  • OrderingCode 1SG065HH1F35E2VG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH2F35I2LG

  • MM# 999LJZ
  • SPECCode SRGPU
  • OrderingCode 1SG065HH2F35I2LG
  • Stepping A0

Intel® Stratix® 10 GX 650 FPGA 1SG065HH1F35E1VGAS

  • MM# 99A7K3
  • SPECCode SRKB0
  • OrderingCode 1SG065HH1F35E1VGAS
  • Stepping A0

Trade compliance information

  • ECC Varies By Product
  • PCode Varies By Product
  • HTS Varies By Product

PCN/MDDS Information

SRKB0

SRKB1

SRKB2

SRKB3

SRKB5

SRGPZ

SRGPY

SRGPX

SRGQ0

SRGPN

SRGPM

SRGPL

SRGPK

SRGPJ

SRKB6

SRGPW

SRKB7

SRGPV

SRKB8

SRGPU

SRGQ5

SRGPT

SRGQ4

SRGPS

SRKAY

SRGPR

SRKAZ

SRGQ3

SRGQ2

SRGPQ

SRGQ1

SRGPP

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.