Intel® Stratix® 10 TX 2800 FPGA
Specifications
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Essentials
-
Product Collection
Intel® Stratix® 10 TX FPGA
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Marketing Status
Launched
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Launch Date
Q1'18
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Lithography
14 nm
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Resources
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Logic Elements (LE)
2753000
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Adaptive Logic Modules (ALM)
933120
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Adaptive Logic Module (ALM) Registers
3732480
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Fabric and I/O Phase-Locked Loops (PLLs)
24
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Maximum Embedded Memory
244 Mb
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Digital Signal Processing (DSP) Blocks
5760
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Processor System (HPS)
Quad-core 64-bit ARM* Cortex*-A53
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys
I/O Specifications
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Maximum User I/O Count†
440
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
216
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Maximum Non-Return to Zero (NRZ) Transceivers†
144
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Maximum Non-Return to Zero (NRZ) Data Rate†
28.9 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
60
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
57.8 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3, 10/25/100G Ethernet
Advanced Technologies
Package Specifications
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Package Options
F2397, F2912
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Intel® Stratix® 10 TX 2800 FPGA 1ST280EY1F55I2LGAS
- MM# 999G66
- Spec Code SRFTY
- Ordering Code 1ST280EY1F55I2LGAS
- Stepping C2
Intel® Stratix® 10 TX 2800 FPGA 1ST280EY2F55I2LGAS
- MM# 999G69
- Spec Code SRFU1
- Ordering Code 1ST280EY2F55I2LGAS
- Stepping C2
Intel® Stratix® 10 TX 2800 FPGA 1ST280EY1F55I2LGBK
- MM# 99A72X
- Spec Code SRK7V
- Ordering Code 1ST280EY1F55I2LGBK
- Stepping C2
Intel® Stratix® 10 TX 2800 FPGA 1ST280EU1F50I2LGBK
- MM# 99A7DK
- Spec Code SRK8W
- Ordering Code 1ST280EU1F50I2LGBK
- Stepping C2
Intel® Stratix® 10 TX 2800 FPGA 1ST280EU2F50I2LGBK
- MM# 99A7DN
- Spec Code SRK8Z
- Ordering Code 1ST280EU2F50I2LGBK
- Stepping C2
Intel® Stratix® 10 TX 2800 FPGA 1ST280EY2F55I2LGBK
- MM# 99A7DX
- Spec Code SRK94
- Ordering Code 1ST280EY2F55I2LGBK
- Stepping C2
Intel® Stratix® 10 TX 2800 FPGA 1ST280EY1F55E2LPBK
- MM# 99A7JJ
- Spec Code SRKAW
- Ordering Code 1ST280EY1F55E2LPBK
- Stepping C2
Intel® Stratix® 10 TX 2800 FPGA 1ST280EU2F50E2VGNE
- MM# 99AKX6
- Spec Code SRL0X
- Ordering Code 1ST280EU2F50E2VGNE
- Stepping C2
Trade compliance information
- ECCN 5A002U
- CCATS G178951
- US HTS 8542390001
PCN Information
SRL0X
- 99AKX6 PCN
SRESD
- 984461 PCN
SRF0D
- 986669 PCN
SRFU5
- 999G6F PCN
SRFU4
- 999G6D PCN
SRFU2
- 999G6A PCN
SRFU1
- 999G69 PCN
SRFU0
- 999G68 PCN
SRFTZ
- 999G67 PCN
SRKAW
- 99A7JJ PCN
SRFTY
- 999G66 PCN
SRFTX
- 999G65 PCN
SRFU9
- 999G6K PCN
SRFU8
- 999G6J PCN
SRFU7
- 999G6H PCN
SRFU6
- 999G6G PCN
SRK95
- 99A7DZ PCN
SRK96
- 99A7F0 PCN
SRK8V
- 99A7DH PCN
SRK8W
- 99A7DK PCN
SRK8X
- 99A7DL PCN
SRK8Y
- 99A7DM PCN
SREYT
- 986371 PCN
SRK8Z
- 99A7DN PCN
SREYS
- 986370 PCN
SRK91
- 99A7DR PCN
SRK92
- 99A7DV PCN
SRK93
- 99A7DW PCN
SRK94
- 99A7DX PCN
SREYJ
- 986361 PCN
SREYH
- 986360 PCN
SREYG
- 986358 PCN
SREYF
- 986357 PCN
SREYE
- 986356 PCN
SREYD
- 986354 PCN
SREYC
- 986353 PCN
SREYR
- 986369 PCN
SREYQ
- 986368 PCN
SREYK
- 986363 PCN
SRF1Q
- 9999CX PCN
SRF22
- 9999DA PCN
SREY9
- 986349 PCN
SRF1P
- 9999CW PCN
SREY8
- 986347 PCN
SRF1N
- 9999CV PCN
SRK7V
- 99A72X PCN
SRF1M
- 9999CT PCN
SRF1L
- 9999CR PCN
SREYB
- 986351 PCN
SREYA
- 986350 PCN
SRF1X
- 9999D5 PCN
SRF1W
- 9999D4 PCN
SRF1V
- 9999D3 PCN
SRF1U
- 9999D2 PCN
SRF1T
- 9999D1 PCN
SRF25
- 9999DF PCN
SRF1S
- 9999D0 PCN
SRF24
- 9999DD PCN
SRF1R
- 9999CZ PCN
SRF23
- 9999DC PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.