Intel® Stratix® 10 TX 1100 FPGA
Specifications
Compare Intel® Products
Essentials
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Product Collection
Intel® Stratix® 10 TX FPGA
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Marketing Status
Launched
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Launch Date
Q1'18
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Lithography
14 nm
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Resources
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Logic Elements (LE)
1325000
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Adaptive Logic Modules (ALM)
449280
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Adaptive Logic Module (ALM) Registers
1797120
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Fabric and I/O Phase-Locked Loops (PLLs)
16
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Maximum Embedded Memory
114 Mb
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Digital Signal Processing (DSP) Blocks
2592
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Processor System (HPS)
Quad-core 64-bit ARM* Cortex*-A53
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys
I/O Specifications
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Maximum User I/O Count†
440
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
216
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Maximum Non-Return to Zero (NRZ) Transceivers†
72
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Maximum Non-Return to Zero (NRZ) Data Rate†
28.9 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
24
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
57.8 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3, 10/25/100G Ethernet
Advanced Technologies
Package Specifications
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Package Options
F1760, F2397
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Intel® Stratix® 10 TX 1100 FPGA 1ST110EN1F43I1VGBK
- MM# 99A7NA
- Spec Code SRKC8
- Ordering Code 1ST110EN1F43I1VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110EN1F43I2LGBK
- MM# 99A7NC
- Spec Code SRKC9
- Ordering Code 1ST110EN1F43I2LGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110EN1F43I2VGBK
- MM# 99A7ND
- Spec Code SRKCA
- Ordering Code 1ST110EN1F43I2VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110EN2F43I1VGBK
- MM# 99A7NF
- Spec Code SRKCB
- Ordering Code 1ST110EN2F43I1VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110EN2F43I2LGBK
- MM# 99A7NG
- Spec Code SRKCC
- Ordering Code 1ST110EN2F43I2LGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110EN2F43I2VGBK
- MM# 99A7NH
- Spec Code SRKCD
- Ordering Code 1ST110EN2F43I2VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110EN3F43I3VGBK
- MM# 99A7NJ
- Spec Code SRKCE
- Ordering Code 1ST110EN3F43I3VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES2F50E2LGBK
- MM# 99A7NP
- Spec Code SRKCK
- Ordering Code 1ST110ES2F50E2LGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES1F50I1VGBK
- MM# 99A7NR
- Spec Code SRKCL
- Ordering Code 1ST110ES1F50I1VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES1F50I2LGBK
- MM# 99A7NT
- Spec Code SRKCM
- Ordering Code 1ST110ES1F50I2LGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES1F50I2VGBK
- MM# 99A7NV
- Spec Code SRKCN
- Ordering Code 1ST110ES1F50I2VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES2F50I1VGBK
- MM# 99A7P2
- Spec Code SRKCP
- Ordering Code 1ST110ES2F50I1VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES2F50I2LGBK
- MM# 99A7PD
- Spec Code SRKCQ
- Ordering Code 1ST110ES2F50I2LGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES2F50I2VGBK
- MM# 99A7PG
- Spec Code SRKCR
- Ordering Code 1ST110ES2F50I2VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES3F50I3VGBK
- MM# 99A7PX
- Spec Code SRKCS
- Ordering Code 1ST110ES3F50I3VGBK
- Stepping A1
Intel® Stratix® 10 TX 1100 FPGA 1ST110ES2F50E2VGNE
- MM# 99C20X
- Spec Code SRM6K
- Ordering Code 1ST110ES2F50E2VGNE
- Stepping A1
Trade compliance information
- ECCN 5A002U
- CCATS G178951
- US HTS 8542390001
PCN Information
SRFJ9
- 999FKR PCN
SRKCP
- 99A7P2 PCN
SRFJ8
- 999FKP PCN
SRKCQ
- 99A7PD PCN
SRFJ7
- 999FKN PCN
SRKCR
- 99A7PG PCN
SRFJ6
- 999FKM PCN
SRKCS
- 99A7PX PCN
SRFJ5
- 999FKL PCN
SRFJ4
- 999FKK PCN
SRFJ3
- 999FKJ PCN
SRFJB
- 999FKV PCN
SRFJA
- 999FKT PCN
SRKCK
- 99A7NP PCN
SRKCL
- 99A7NR PCN
SRKCM
- 99A7NT PCN
SRKCN
- 99A7NV PCN
SRKCA
- 99A7ND PCN
SRKCB
- 99A7NF PCN
SRKCC
- 99A7NG PCN
SRKCD
- 99A7NH PCN
SRKCE
- 99A7NJ PCN
SRFJ2
- 999FKH PCN
SRFJ1
- 999FKG PCN
SRKC8
- 99A7NA PCN
SRFJ0
- 999FKF PCN
SRKC9
- 99A7NC PCN
SRM6K
- 99C20X PCN
SRFHX
- 999FKA PCN
SRFHW
- 999FK9 PCN
SRFHV
- 999FK8 PCN
SRFHU
- 999FK7 PCN
SRFHT
- 999FK6 PCN
SRFHS
- 999FK5 PCN
SRFHR
- 999FK4 PCN
SRFHZ
- 999FKD PCN
SRFHY
- 999FKC PCN
SRGVS
- 999N41 PCN
SRGVR
- 999N40 PCN
SRGVQ
- 999N3Z PCN
SRGVP
- 999N3X PCN
SRGVN
- 999N3W PCN
SRGVX
- 999N47 PCN
SRGVM
- 999N3V PCN
SRGYX
- 999PJM PCN
SRGYW
- 999PJL PCN
SRGYV
- 999PJK PCN
SRGYU
- 999PJJ PCN
SRGYT
- 999PJH PCN
SRGYS
- 999PJG PCN
SRGYR
- 999PJF PCN
SRGYY
- 999PJN PCN
SRFJJ
- 999FL3 PCN
SRFJH
- 999FL2 PCN
SRFJG
- 999FL1 PCN
SRFJF
- 999FL0 PCN
SRFJE
- 999FKZ PCN
SRFJD
- 999FKX PCN
SRFJC
- 999FKW PCN
SRFJN
- 999FL7 PCN
SRFJM
- 999FL6 PCN
SRFJL
- 999FL5 PCN
SRFJK
- 999FL4 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.