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  • Brand Name: Core Ultra

  • Product Number: 6526Y

  • Ordering Code: PK8072205559500

  • SPEC Code: SRN6N

  • Code Name: Emerald Rapids

Intel® Stratix® 10 TX 400 FPGA

Specifications

Export specifications

Essentials

Resources

I/O Specifications

Advanced Technologies

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35E1VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35E2LG

  • MM# 999LDK
  • Spec Code SRGNL
  • Ordering Code 1ST040EH1F35E2LG
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I1VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35E1VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35E2LG

  • MM# 999LDZ
  • Spec Code SRGNQ
  • Ordering Code 1ST040EH2F35E2LG
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I1VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35E3XG

  • MM# 999LF8
  • Spec Code SRGNT
  • Ordering Code 1ST040EH3F35E3XG
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3XG

  • MM# 999LF9
  • Spec Code SRGNU
  • Ordering Code 1ST040EH3F35I3XG
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35E2VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35E2VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35E3VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2LG

  • MM# 999LG4
  • Spec Code SRGNY
  • Ordering Code 1ST040EH1F35I2LG
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3VG

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2LG

  • MM# 999LGP
  • Spec Code SRGP0
  • Ordering Code 1ST040EH2F35I2LG
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I1VGAS

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2LGAS

  • MM# 999RP0
  • Spec Code SRH1H
  • Ordering Code 1ST040EH1F35I2LGAS
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2VGAS

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I1VGAS

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2LGAS

  • MM# 999RPC
  • Spec Code SRH1L
  • Ordering Code 1ST040EH2F35I2LGAS
  • Stepping A0
  • MDDS Content IDs 795952,  813820

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2VGAS

Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3VGAS

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I1VGBK

  • MM# 99A730
  • Spec Code SRK7X
  • Ordering Code 1ST040EH1F35I1VGBK
  • Stepping A0
  • MDDS Content IDs 795952,  800035

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2LGBK

  • MM# 99A731
  • Spec Code SRK7Y
  • Ordering Code 1ST040EH1F35I2LGBK
  • Stepping A0
  • MDDS Content IDs 795952

Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2VGBK

  • MM# 99A732
  • Spec Code SRK7Z
  • Ordering Code 1ST040EH1F35I2VGBK
  • Stepping A0
  • MDDS Content IDs 795952,  800035

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I1VGBK

  • MM# 99A733
  • Spec Code SRK80
  • Ordering Code 1ST040EH2F35I1VGBK
  • Stepping A0
  • MDDS Content IDs 795952,  800035

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2LGBK

  • MM# 99A734
  • Spec Code SRK81
  • Ordering Code 1ST040EH2F35I2LGBK
  • Stepping A0
  • MDDS Content IDs 795952

Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2VGBK

  • MM# 99A735
  • Spec Code SRK82
  • Ordering Code 1ST040EH2F35I2VGBK
  • Stepping A0
  • MDDS Content IDs 795952,  800035

Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3VGBK

  • MM# 99A736
  • Spec Code SRK83
  • Ordering Code 1ST040EH3F35I3VGBK
  • Stepping A0
  • MDDS Content IDs 795952,  800035

Trade compliance information

  • ECCN 5A002U
  • CCATS G178951
  • US HTS 8542390001

PCN Information

SRH1G

SRGP0

SRGNZ

SRGNY

SRGNX

SRGNW

SRGNV

SRGNM

SRGNL

SRH1N

SRGNK

SRH1M

SRH1L

SRH1K

SRH1J

SRK7X

SRK7Y

SRH1H

SRK7Z

SRGNU

SRGNT

SRGNS

SRGNR

SRGNQ

SRK80

SRGNP

SRK81

SRK82

SRGNN

SRK83

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Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count†

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers†

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate†

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†

The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†

The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.

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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.

Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.

Refer to Datasheet for formal definitions of product properties and features.

‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.

“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.