Intel® Stratix® 10 TX 400 FPGA
Specifications
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Essentials
-
Product Collection
Intel® Stratix® 10 TX FPGA
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Off Roadmap
No
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Status
Launched
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Launch Date
Q1'18
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Publication Date
Tuesday, December 29, 2020
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Lithography
14 nm
Resources
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Logic Elements (LE)
378000
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Adaptive Logic Modules (ALM)
128160
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Adaptive Logic Module (ALM) Registers
512640
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Fabric and I/O Phase-Locked Loops (PLLs)
8
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Maximum Embedded Memory
32 Mb
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Digital Signal Processing (DSP) Blocks
648
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Processor System (HPS)
Quad-core 64-bit ARM* Cortex*-A53
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys
I/O Specifications
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Maximum User I/O Count†
392
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
192
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Maximum Non-Return to Zero (NRZ) Transceivers†
24
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Maximum Non-Return to Zero (NRZ) Data Rate†
28.9 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
12
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
57.8 Gbps
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Transceiver Protocol Hard IP
10/25/100G Ethernet
Advanced Technologies
Package Specifications
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Package Options
F1152
Supplemental Information
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Additional Information
View now
Ordering and Compliance
Ordering and spec information
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35E2VG
- MM# 999LFC
- SPECCode SRGNV
- OrderingCode 1ST040EH1F35E2VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3VG
- MM# 999LGN
- SPECCode SRGNZ
- OrderingCode 1ST040EH3F35I3VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35E2LG
- MM# 999LDK
- SPECCode SRGNL
- OrderingCode 1ST040EH1F35E2LG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2VGBK
- MM# 99A735
- SPECCode SRK82
- OrderingCode 1ST040EH2F35I2VGBK
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I1VGBK
- MM# 99A733
- SPECCode SRK80
- OrderingCode 1ST040EH2F35I1VGBK
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2VG
- MM# 999LDT
- SPECCode SRGNN
- OrderingCode 1ST040EH1F35I2VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2LGBK
- MM# 99A734
- SPECCode SRK81
- OrderingCode 1ST040EH2F35I2LGBK
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I1VG
- MM# 999LF6
- SPECCode SRGNR
- OrderingCode 1ST040EH2F35I1VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2VG
- MM# 999LF7
- SPECCode SRGNS
- OrderingCode 1ST040EH2F35I2VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35E2LG
- MM# 999LDZ
- SPECCode SRGNQ
- OrderingCode 1ST040EH2F35E2LG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2LGBK
- MM# 99A731
- SPECCode SRK7Y
- OrderingCode 1ST040EH1F35I2LGBK
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35E3VG
- MM# 999LFP
- SPECCode SRGNX
- OrderingCode 1ST040EH3F35E3VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3VGBK
- MM# 99A736
- SPECCode SRK83
- OrderingCode 1ST040EH3F35I3VGBK
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35E1VG
- MM# 999LDJ
- SPECCode SRGNK
- OrderingCode 1ST040EH1F35E1VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35E3XG
- MM# 999LF8
- SPECCode SRGNT
- OrderingCode 1ST040EH3F35E3XG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3XG
- MM# 999LF9
- SPECCode SRGNU
- OrderingCode 1ST040EH3F35I3XG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I1VG
- MM# 999LDL
- SPECCode SRGNM
- OrderingCode 1ST040EH1F35I1VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2LG
- MM# 999LGP
- SPECCode SRGP0
- OrderingCode 1ST040EH2F35I2LG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35E1VG
- MM# 999LDX
- SPECCode SRGNP
- OrderingCode 1ST040EH2F35E1VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35E2VG
- MM# 999LFK
- SPECCode SRGNW
- OrderingCode 1ST040EH2F35E2VG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I1VGBK
- MM# 99A730
- SPECCode SRK7X
- OrderingCode 1ST040EH1F35I1VGBK
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2VGBK
- MM# 99A732
- SPECCode SRK7Z
- OrderingCode 1ST040EH1F35I2VGBK
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2LG
- MM# 999LG4
- SPECCode SRGNY
- OrderingCode 1ST040EH1F35I2LG
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH3F35I3VGAS
- MM# 999RPF
- SPECCode SRH1N
- OrderingCode 1ST040EH3F35I3VGAS
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2LGAS
- MM# 999RP0
- SPECCode SRH1H
- OrderingCode 1ST040EH1F35I2LGAS
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I1VGAS
- MM# 999RNZ
- SPECCode SRH1G
- OrderingCode 1ST040EH1F35I1VGAS
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2VGAS
- MM# 999RPD
- SPECCode SRH1M
- OrderingCode 1ST040EH2F35I2VGAS
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH1F35I2VGAS
- MM# 999RP7
- SPECCode SRH1J
- OrderingCode 1ST040EH1F35I2VGAS
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I1VGAS
- MM# 999RPA
- SPECCode SRH1K
- OrderingCode 1ST040EH2F35I1VGAS
- Stepping A0
Intel® Stratix® 10 TX 400 FPGA 1ST040EH2F35I2LGAS
- MM# 999RPC
- SPECCode SRH1L
- OrderingCode 1ST040EH2F35I2LGAS
- Stepping A0
Trade compliance information
- ECC Varies By Product
- PCode Varies By Product
- HTS Varies By Product
PCN/MDDS Information
SRH1G
- 999RNZ PCN
SRGP0
- 999LGP PCN
SRGNZ
- 999LGN PCN
SRGNY
- 999LG4 PCN
SRGNX
- 999LFP PCN
SRGNW
- 999LFK PCN
SRGNV
- 999LFC PCN
SRGNM
- 999LDL PCN
SRGNL
- 999LDK PCN
SRH1N
- 999RPF PCN
SRGNK
- 999LDJ PCN
SRH1M
- 999RPD PCN
SRH1L
- 999RPC PCN
SRH1K
- 999RPA PCN
SRK7X
- 99A730 PCN
SRH1J
- 999RP7 PCN
SRK7Y
- 99A731 PCN
SRK7Z
- 99A732 PCN
SRH1H
- 999RP0 PCN
SRGNU
- 999LF9 PCN
SRGNT
- 999LF8 PCN
SRGNS
- 999LF7 PCN
SRGNR
- 999LF6 PCN
SRK80
- 99A733 PCN
SRGNQ
- 999LDZ PCN
SRK81
- 99A734 PCN
SRGNP
- 999LDX PCN
SRK82
- 99A735 PCN
SRGNN
- 999LDT PCN
SRK83
- 99A736 PCN
Drivers and Software
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Technical Documentation
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
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Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.